DRAM memory having vertically arranged selection transistors
View Patent ↗Memory cell having a trench capacitor that is constructed in a lower region of a substantially perpendicular trench hole, and which comprises an inner and an outer electrode, a dielectric layer being arranged between the inner and the outer electrodes, a vertical selection transistor that has a substantially perpendicular channel region, which is constructed adjacent to an upper region of the trench hole and which connects the inner electrode of the trench capacitor to a bit line, it being possible to construct a conductive channel as a function of the potential of a word line in the channel region, the channel region partially enclosing the trench hole in its upper region, and the associated work line at least partially surrounding the channel region.
1. A memory cell, comprising:
a cylindrical trench capacitor formed in a lower portion of a trench hole, the cylindrical trench capacitor comprising:
an inner electrode;
an outer electrode; and
a dielectric layer disposed between the inner electrode and the outer electrode; and
a vertical selection transistor located above the cylindrical trench capacitor and comprising a first source-drain electrode, a second source-drain electrode and an interposed channel area formed between the source-drain electrodes, the first source-drain electrode being connected to the inner electrode of the trench capacitor, and the second source-drain electrode being connected to a bit line;
wherein a conductive channel is formed in the channel area as a function of a potential of a word line in order to connect the inner electrode of the trench capacitor to the bit line;
wherein the channel area at least partially surrounds the trench hole without completely surrounding the trench hole;
wherein the trench hole is defined at least in part by two side walls arranged at an angle to one another; and
wherein the channel area at least partially surrounds the two side walls of the trench hole.
2. The memory cell of claim 1 , wherein the channel area extends beyond an upper end of the inner electrode.
3. The memory cell of claim 1 , wherein the trench hole has a substantially polygonal cross section and wherein the two side walls of the trench hole meet at an angle to form an edge oriented substantially in the direction of the bit line and disposed substantially centrally below the bit line.
4. The memory cell of claim 1 , wherein the inner electrode comprises a filling in the trench hole and wherein the outer electrode is formed around the trench hole.
5. The memory cell of claim 1 , wherein the second source-drain electrode is a diffused portion of a substrate and is connected directly to the bit line.
6. The memory cell of claim 1 , wherein the vertical selection transistor is located at the upper portion of the trench hole.
7. The memory cell of claim 1 , wherein the bit line extends substantially in the center above the trench hole.
8. The memory cell of claim 1 , wherein the first source-drain area is connected as a buried strap area with the inner electrode of the trench capacitor.
9. The memory cell of claim 1 , wherein the word line is implemented as a buried word line in a substrate and which extends from a predetermined depth to an upper surface of the substrate.
10. The memory cell of claim 1 , wherein the upper portion of the trench hole, which is partially surrounded by the channel area, is filled with a material which, due to at least one of its physical and electrical characteristics, influences the conductivity of the channel area.
11. The memory cell of claim 1 , wherein the trench hole and the channel area have a substantially polygonal cross section.
12. The memory cell of claim 11 , wherein the polygonal cross section is one of square and rectangular.
13. The memory cell of claim 1 , wherein the channel area extends vertically through the word line.
14. The memory cell of claim 13 , wherein the channel area is formed in a portion of a substrate.