Methods of manufacturing MOSFETs in semiconductor devices
View Patent ↗Methods of fabricating MOSFETs in semiconductor/r devices are disclosed. One example method may include forming an isolation layer on a semiconductor substrate and forming a capping layer thereon, forming an epitaxial active region which is not covered with the isolation layer on said semiconductor substrate by using selectively epitaxial growth, and forming a gate dielectric layer and a gate electrode on said epitaxial active region, sequentially. The example method may also include forming a source/drain plug spaced apart from the both sides of said gate electrode in said epitaxial active region, forming a source/drain into said epitaxial active region on which said source/drain plug is formed, forming an interlayer dielectric layer on the entire surface of the resultant structure after the source/drain is formed; and forming contacts in said interlayer dielectric layer, wherein said contacts are connected to said gate electrode and said source/drain plug, respectively.
1. A method for fabricating a MOSFET in a semiconductor device, comprising:
forming an isolation layer on a semiconductor substrate and forming a capping layer thereon;
forming an epitaxial active region which is not covered with the isolation layer on said semiconductor substrate by using selective epitaxial growth;
forming a gate dielectric layer and a gate electrode on said epitaxial active region, sequentially;
forming a spacer dielectric layer on sidewalls of said gate electrode and patterning said gate dielectric layer by using said gate electrode and said spacer dielectric layer as a mask, after the gate electrode is formed;
forming a source/drain plug spaced apart from the both sides of said gate electrode on said epitaxial active region by another selective epitaxial growth;
forming a source/drain by a donant diffusion from said source/drain plug into said epitaxial active region on which said source/drain plug is formed;
removing said spacer dielectric layer and a portion of said gate dielectric layer, after said source/drain is formed;
forming an interlayer dielectric layer on the entire surface of the resultant structure after the source/drain is formed; and
forming contacts in said interlayer dielectric layer, wherein said contacts are connected to said gate electrode and said source/drain plug, respectively.
2. A method as defined by claim 1 , wherein said source/drain plug comprises a doped silicon layer.
3. A method as defined by claim 2 , wherein forming said source/drain comprises performing an annealing process.
4. A method as defined by claim 1 , wherein said source/drain plug comprises a silicon layer doped with an n+30 /p+30 +0 dopant.
5. A method as defined by claim 4 , wherein forming said source/drain comprises performing an ion implantation process to said source/drain plug and an annealing process, sequentially.
6. A method as defined by claim 1 , before said interlayer dielectric layer is formed, further comprising:
forming a lightly doped drain (“LDD”) region into said epitaxial active region between said gate electrode and said source/drain plug.
7. A method as defined by claim 6 , wherein said lightly doped drain (“LDD”) region comprises performing an ion implantation process.
8. A method as defined by claim 1 , wherein said interlayer dielectric layer comprises a borosilicate glass (“BSG”) or a phosphosilicate glass (“PSG”).
9. A method as defined by claim 8 , further comprising:
forming a lightly doped drain (“LDD”) region into said epitaxial active region between said gate electrode and said source/drain plug by performing an annealing process, after forming said interlayer dielectric layer.