IP Library Granted Patent US 7,074,702
Granted Patent B2
US 7,074,702 · App. 10/746,837 · Granted Jul 11, 2006

Methods of manufacturing semiconductor devices

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Quick Facts
Patent No.
US 7,074,702
App. No.
10/746,837
Granted
Jul 11, 2006
Kind
B2
Abstract

Disclosed are methods of manufacturing semiconductor devices, which may solve problems such as a short of upper wiring, etc., which are caused by a metal residue generated during chemical mechanical polishing of metallization of the semiconductor device, by depositing a predetermined insulating layer on the metal residue. The method may include forming a first insulating layer having an opening on a semiconductor substrate, depositing a metal layer on the first insulating layer to sufficiently fill the opening, planarizing the metal layer to expose the first insulating layer, forming a second insulating layer on the exposed first insulating layer and the metal layer, selectively etching and removing the second insulating layer to expose the metal layer, and forming a metallization layer on the metal layer.

Claims (10)

1. A method of manufacturing a semiconductor device, comprising:

forming a first insulating layer having an opening on a semiconductor substrate, wherein the first insulating layer is formed of a first material;

depositing a metal layer on the first insulating layer to sufficiently fill the opening;

planarizing the metal layer to expose the first insulating layer;

etching the first insulating layer to cause the surface of the metal layer to protrude from a surface of the first insulating layer, wherein the first insulating layer is etched at a depth of 50 to 200 Å;

forming a second insulating layer in contact with the exposed first insulating layer and the metal layer after etching the first insulating layer, wherein the second insulating layer is formed of a second material that is the same material as the first material;

selectively etching and removing the second insulating layer to expose the metal layer; and

forming a metallization layer on the metal layer.

2. A method as defined by claim 1 , wherein the second insulating layer is formed using boro-phospho-silicato glass (BPSG).

3. A method as defined by claim 1 , wherein the second insulating layer is formed at a thickness of 300 to 1000 Å.

Assignments (5)
CHANGE OF NAME Recorded Nov 30, 2017
From: DONGBU HITEK CO., LTD.
To: DB HITEK CO., LTD
Reel/Frame 044555/0913 →
MERGER AND CHANGE OF NAME Recorded Nov 29, 2017
From: DONGBU ELECTRONICS CO., LTD.; DONGBU HITEK CO., LTD.
To: DONGBU HITEK CO., LTD.
Reel/Frame 044533/0523 →
CHANGE OF NAME Recorded Jun 6, 2006
From: DONGBU ANAM SEMICONDUCTORS, INC
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017718/0964 →
MERGER Recorded May 31, 2005
From: DONGBU SEMICONDUCTOR INC.
To: DONGBUANAM SEMICONDUCTOR, INC.
Reel/Frame 016593/0667 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 20, 2004
From: KIM, SEUNG HYUN
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 014891/0165 →