IP Library Granted Patent US 7,135,371
Granted Patent B2
US 7,135,371 · App. 10/747,602 · Granted Nov 14, 2006

Methods of fabricating semiconductor devices

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Quick Facts
Patent No.
US 7,135,371
App. No.
10/747,602
Granted
Nov 14, 2006
Kind
B2
Abstract

Methods of fabricating semiconductor devices are disclosed. One example method includes forming a gate oxide and a gate electrode on a semiconductor substrate; performing a first ion implantation process for the formation of an LDD (lightly doped drain) region in the substrate; forming spacers on the sidewalls of the gate electrode; performing a second ion implantation process for the formation of a junction region in the substrate using the spacers as mask; forming a trench for device isolation by removing selectively the top portion of the substrate between the spacers; forming a sidewall oxide layer on the resulting substrate; forming a diffusion barrier on the sidewall oxide layer; depositing a gap filling insulation layer over the diffusion barrier; planarizing the gap filling insulating layer; and removing selectively some part of the gap filling insulation layer to form contact holes.

Claims (15)

1. A method for fabricating a semiconductor device comprising:

forming a gate oxide and a gate electrode on a semiconductor substrate;

performing a first ion implantation process for the formation of a (lightly doped drain) LDD region in the substrate;

forming spacers on the sidewalls of the gate electrode;

performing a second ion implantation process for the formation of a junction region in the substrate using the spacers as a mask;

forming a trench for device isolation by removing selectively the top portion of the substrate between the spacers;

forming an oxide layer on the whole substrate except on the spacers;

forming a diffusion barrier on the resulting substrate;

depositing a gap filling insulation layer over the diffusion barrier;

planarizing the gap filling insulating layer; and removing selectively some part of the gap filling insulation layer to form contact holes.

2. A method as defined by claim 1 , wherein the gap filling insulation layer is formed of boro-phosphosilicate glass (BPSG).

3. A method as defined by claim 1 , wherein the diffusion barrier is formed of amorphous silicon.

4. A method as defined by claim 1 , wherein the diffusion barrier is an N-doped oxide.

5. A method as defined by claim 1 , wherein the gap filling insulation layer is formed of undoped silicate glass (USG).

6. A method as defined by claim 1 , wherein the gap filling insulation layer is used as both a device isolation layer and an interlayer insulation layer.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 28, 2014
From: DONGBU HITEK CO., LTD.
To: DSS TECHNOLOGY MANAGEMENT, INC.
Reel/Frame 033035/0680 →
CHANGE OF NAME Recorded Jun 6, 2006
From: DONGBU ANAM SEMICONDUCTORS, INC
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017718/0964 →
MERGER Recorded May 31, 2005
From: DONGBU SEMICONDUCTOR INC.
To: DONGBUANAM SEMICONDUCTOR, INC.
Reel/Frame 016593/0667 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 2, 2004
From: HAN, CHANG HUN; KEUM, DONG YEAL
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 014939/0852 →