Methods of manufacturing and-type flash memory devices
View Patent ↗Example methods of manufacturing an AND-type flash memory device are disclosed. One example method may include forming a tunnel oxide layer and a first polysilicon layer in sequence on a silicon substrate; forming a floating gate by removing some part of the first polysilicon layer; forming a source/drain region at both sides of the floating gate by implanting ions into the substrate; forming spacers on sidewalls of the floating gate; depositing a sacrificial layer on the resulting substrate; exposing some part of the substrate and the floating gate; forming a first trench on the exposed part of the substrate and a second trench on the exposed part of the floating gate; depositing an oxide layer to fill the first and second trenches with the oxide layer; removing the oxide layer and the sacrificial layer through a fourth etching process until the floating gate is exposed; removing the spacers and the remaining sacrificial layer to form the floating gate with the second trench and a trench-type device isolation layer; and depositing a gate insulating layer and a second polysilicon layer to form a control gate in sequence on the resulting substrate.
1. A method for manufacturing a flash memory device, the method comprising:
forming a tunnel oxide layer on a semiconductor substrate;
forming a floating gate on the tunnel oxide layer;
forming a source/drain region at both sides of the floating gate by implanting ions into the semiconductor substrate including the floating gate;
forming spacers on sidewalls of the floating gate;
depositing a sacrificial layer on the resulting substrate;
exposing some part of the substrate and the floating gate by removing some part of the sacrificial layer and the tunnel oxide layer;
forming a first trench on the exposed part of the substrate and a second trench on the exposed part of the floating gate;
depositing an oxide layer to fill the first and second trenches with the oxide layer;
removing the oxide layer and the sacrificial layer until the floating gate is exposed;
removing the spacers and the remaining sacrificial layer to form a floating gate with the second trench and a trench-type device isolation layer; and
depositing a gate insulating layer and a second polysilicon layer for a control gate on the resulting substrate.
2. A method as defined by claim 1 , wherein the first polysilicon layer is formed more thickly than the device isolation layer.
3. A method as defined by claim 2 , wherein the first polysilicon layer is 300 Å~2500 Å thicker than the device isolation layer.
4. A method as defined by claim 1 , wherein the spacers are formed of nitride.
5. A method as defined by claim 1 , wherein the sacrificial layer is formed of one of TEOS oxides, BPSG, PSG, and HDP oxides.
6. A method as defined by claim 1 , wherein the oxide layer is formed of one of TEOS oxides, BPSG, PSG, and HDP oxides.
7. A method as defined by claim 1 , wherein the oxide layer and the sacrificial layer are removed through a CMP process or an etch back process until the floating gate is exposed.
8. A method as defined by claim 1 , wherein the spacers and the remaining sacrificial layer is removed through a wet etching process using phosphoric acid at a temperature higher than 70° C.