Methods for fabricating nonvolatile memory devices
View Patent ↗Methods of fabricating nonvolatile memory devices are disclosed. A disclosed method comprises forming a trench isolation layer on a substrate; forming an oxide layer and a polysilicon layer; forming a sacrificial layer on the polysilicon layer; forming a photoresist pattern on the sacrificial layer; performing an etching process using the photoresist pattern as a mask and, at the same time, attaching polymers on sidewalls of the etched sacrificial layer to form polymer layers, the polymers being generated from the etching of the sacrificial layer; and forming a floating gate and a tunnel oxide by removing part of the polysilicon layer and the oxide layer using the polymer layers and the photoresist pattern as a mask. The disclosed method can increase the width of a floating gate by using polymer layers in fabricating a two-bit type cell, thereby ensuring a higher coupling ratio compared to the coupling ratio of a conventional two-bit type cell.
1. A method for fabricating a nonvolatile memory device comprising:
forming an isolation layer and a non-active region in a semiconductor substrate;
forming an oxide layer and a polysilicon layer on the substrate;
forming a sacrificial layer on the polysilicon layer;
patterning the sacrificial layer to form polymer layers on sidewalls of the sacrificial layer,
wherein patterning the sacrificial layer to form polymer layers on sidewalls of the sacrificial layer comprises:
forming a photoresist pattern on the sacrificial layer, and
etching portion of the sacrificial layer through the photoresist pattern, the polymer layers being generated from the etching of the sacrificial layer; and
forming a floating gate and a tunnel oxide using the sacrificial layer and the polymer layers as an etching mask.
2. A method as defined in claim 1 , further comprising:
removing the polymer layers and the sacrificial layer; and
forming an insulating layer and a polysilicon layer over the substrate, the floating gate, and the tunnel oxide.
3. A method as defined in claim 1 , wherein the sacrificial layer is formed of one selected from the group consisting of TEOS (tetraethyl orthosilicate) oxides and nitride.
4. A method as defined in clalm 1 , wherein a space between two adjacent polymer layers is between 300 Å and 1200 Å.
5. A method as defined in claim 1 , wherein the polymer layers on the sidewalls of the sacrificial layer are separated by less than a lithographic minimum feature size.
6. A method for fabricating a nonvolatile memory device comprising:
forming an isolation layer and a non-active region in a semiconductor substrate;
fanning an oxide layer and a polysilicon layer on the substrate;
forming a first sacrificial layer on the polysilicon layer;
forming a second sacrificial layer on the tb-st sacrificial layer;
etching the first sacrificial layer using the second sacrificial layer as a mask to form polymer layers on sidewalls of the first and the second sacrificial layers, the polymer layers being generated from the etching of the first sacrificial layer; and
forming a floating gate and a tunnel oxide using the first and the second sacrificial layers and the polymer layers as an etching mask.
7. A method as defined in claim 6 , further comprising:
removing the polymer layers, the first sacrificial layer and the second sacrificial layer; and
forming an insulating layer and a polysilicon layer over the substrate, the floating gate, and the tunnel oxide.
8. A method as defined in claim 6 , wherein the polymer layers on the sidewalls of the first and the second sacrificial layers are separated by less than a lithographic minimum feature size.
9. A method as defined in claim 6 , wherein the second sacrificial layer comprises a patterned photoresistive material.