Semiconductor integrated circuit device and the process of manufacturing the same having poly-silicon plug, wiring trenches and bit lines formed in the wiring trenches having a width finer than a predetermined size
View Patent ↗A memory cell of a DRAM is reduced in size by making the width of a bit line finer than the minimum size determined by the limit of resolution of a photolithography. The bit line is made fine by forming a silicon oxide film on the inside wall of a wiring trench formed in a silicon oxide film and by forming the bit line inside the silicon oxide film. The silicon oxide film formed in the trench is deposited so that the silicon oxide film has a thickness thinner than half the width of the wiring trench and in the fine gap inside the silicon oxide film is buried a metal film to be the material of the bit line.
1. A semiconductor integrated circuit device comprising:
a semiconductor substrate,
wherein said semiconductor substrate on a main surface thereof, comprises:
a memory cell including a MISFET for selecting a memory cell which is provided with a gate electrode integrally formed with a word line,
a first insulating film formed over the MISFET for selecting said memory cell,
a first hole formed in the first insulating film exposing one of a pair of source and drain region of the MISFET and part of a device isolation region,
a first plug buried in a second hole and electrically connected to other one of said pair of source and drain region of the MISFET for selecting said memory cell,
a second insulating film formed over the first insulating film and the first plug,
a trench formed in the second insulating film and over the first plug, and
a bit line and a second plug formed in the trench and in the first hole respectively and electrically connected to the one of said pair of source and drain region,
wherein said bit line and said second plug are comprised of the same metallic material which is commonly buried in the same manufacturing step in both the trench and the first hole,
wherein an upper surface of the bit line and an upper surface of the second insulating film is substantially at a same level, and
wherein a width of said bit line is smaller than a minimum size determined by a limit of resolution of photolithography used to form the trench in which said bit line is formed.
2. The semiconductor integrated circuit device as claimed in claim 1 , wherein the memory cell includes sidewall spacers formed on side wall of the trench, and
wherein the bit line is formed in the trench and inside the sidewall spacers.
3. The semiconductor integrated circuit device as claimed in claim 2 , wherein the sidewall spacer is formed of a silicon oxide film.
4. The semiconductor integrated circuit device as claimed in claim 1 , wherein the first plug is formed of poly-silicon.
5. The semiconductor integrated circuit device as claimed in claim 1 , wherein the bit line is formed of a metal film.
6. The semiconductor integrated circuit device as claimed in claim 5 , wherein the metal film includes a tungsten film.
7. The semiconductor integrated circuit device as claimed in claim 5 , wherein the metal film is formed of a laminated film includes at least a tungsten film and a titanium nitride film.
8. A semiconductor integrated circuit device comprising:
a semiconductor substrate,
wherein said semiconductor substrate on a main surface thereof, comprises:
a memory cell including a MISFET for selecting a memory cell which is provided with a gate electrode integrally formed with a word line extending in a first direction,
a first plug formed in a first contact hole electrically connected to one of a pair of source and drain of the MISFET for selecting said memory cell,
a second plug formed in a second contact hole electrically connected to other one of said pair of source and drain of the MISFET for selecting said memory cell,
a third plug formed in a through hole electrically connected to said second plug, and
a bit line electrically connected to the second plug and extending in a second direction intersecting the first direction via the third plug formed on the second plug as a one conductor with the bit line,
wherein said bit line is formed in a trench having a sidewall spacer between said bit line and a sidewall of said trench,
wherein said bit line and said third plug are comprised of the same metallic material which is commonly buried in the same manufacturing step in both the trench and the through hole, and
wherein the width of the bit line in the first direction is smaller than the interval in the first direction between the neighboring bit lines and smaller than the minimum size determined by the limit of resolution of photolithography used to form said trench.
9. The semiconductor integrated circuit device as claimed in claim 8 , wherein the second contact hole is constituted by a plan pattern having a diameter larger in the first direction than in the second direction,
wherein a part of the second contact hole extends over an active region where the MISFET for selecting a memory cell is formed, and
wherein the other part thereof extends over a device isolating region directly below the bit line.
10. The semiconductor integrated circuit device as claimed in claim 8 , wherein an active region where the MISFET for selecting said memory cell is formed is constituted by a plan pattern extending slenderly along the second direction and having a portion projecting in the first direction at the one side of the center thereof.
11. The semiconductor integrated circuit device as claimed in claim 8 , wherein the first and second plugs are formed of poly-silicon.
12. The semiconductor integrated circuit device as claimed in claim 8 , wherein the bit line is formed of a metal film.
13. The semiconductor integrated circuit device as claimed in claim 12 , wherein the metal film includes a tungsten film.
14. The semiconductor integrated circuit device as claimed in claim 12 , wherein the metal film is formed of a laminated film includes at least a tungsten film and a titanium nitride film.