IP Library Granted Patent US 6,977,432
Granted Patent B2
US 6,977,432 · App. 10/755,414 · Granted Dec 20, 2005

Prefabricated semiconductor chip carrier

Assignee: Quantum Leap Packaging, Inc.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,977,432
App. No.
10/755,414
Granted
Dec 20, 2005
Kind
B2
Abstract

A semiconductor die carrier includes a plurality of electrically insulative side walls; a plurality of electrically conductive leads extending from at least one of the side walls, each of the leads being individually manufactured without use of a lead frame; a semiconductor die positioned such that the electrically conductive leads are disposed at one or more locations around the periphery of the die; and structure for providing electrical connection between the semiconductor die and corresponding ones of the electrically conductive leads. A method of manufacturing a semiconductor die carrier includes the steps of individually manufacturing a plurality of electrically conductive leads without use of a lead frame; extending a plurality of the electrically conductive leads from at least one of a plurality of electrically insulative side walls; positioning a semiconductor die such that the electrically conductive leads are disposed at one or more locations around the periphery of the die; and electrically connecting the semiconductor die to corresponding ones of the electrically conductive leads.

Claims (16)

1. A semiconductor die carrier comprising:

a carrier housing including a plurality of electrically insulative side walls;

a plurality of substantially L-shaped electrically conductive leads extending through at least one of the side walls and arranged in multiple vertically-spaced rows, the leads secured in said at least one side wall by friction, wherein each of the leads includes a mounting surface external of the carrier housing for forming a surface mount electrical connection to a circuit board;

a semiconductor die positioned within said carrier housing such that the electrically conductive leads are disposed at one or more locations around the periphery of the die, said semiconductor die comprising a plurality of bonding pads; and

electrically-conductive bond wiring extending between the bonding pads and the leads for providing electrical connection between the semiconductor die and corresponding ones of the electrically conductive leads.

2. The semiconductor die carrier according to claim 1 , wherein the leads comprise a first group of leads and a second group of leads, the mounting surfaces of the first group of leads are positioned for contacting a first level of the circuit board and the mounting surfaces of the second group of leads are positioned for contacting a second level of the circuit board.

3. The semiconductor die carrier according to claim 1 , further comprising a second semiconductor die positioned within said carrier housing.

4. The semiconductor die carrier according to claim 1 , wherein said carrier housing further comprises a thermally conductive cap.

5. The semiconductor die carrier according to claim 1 , wherein the leads extend from multiple side walls of the carrier housing.

6. The semiconductor die carrier according to claim 1 , wherein the carrier housing encapsulates the semiconductor die.

7. The semiconductor die carrier according to claim 1 , wherein the bond wiring comprises tape-automated bonding.

8. The semiconductor die carrier according to claim 1 , wherein the bond wiring comprises wire bonding.

9. The semiconductor die carrier according to claim 1 , wherein the carrier housing further comprises a floor.

10. The semiconductor die carrier according to claim 4 , wherein the semiconductor die is mounted to the cap.

11. The semiconductor die carrier according to claim 9 , wherein the semiconductor die is mounted to the floor.

12. The semiconductor die carrier according to claim 11 , wherein the floor comprises an indentation for receiving the semiconductor die.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 11, 2012
From: INTERPLEX QLP, INC.
To: IQLP, LLC
Reel/Frame 028028/0221 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 16, 2009
From: INTERPLEX ENGINEERED PRODUCTS, INC.
To: INTERPLEX QLP, INC.
Reel/Frame 022960/0406 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2009
From: QUANTUM LEAP PACKAGING, INC.
To: INTERPLEX ENGINEERED PRODUCTS, INC.
Reel/Frame 022951/0884 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME PREVIOUSLY RECORDED ON REEL 022892 FRAME 0082. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jul 6, 2009
From: QUANTUM LEAP PACKAGING, INC.
To: INTERPLEX ENGINEERED PRODUCTS, INC.
Reel/Frame 022915/0962 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2009
From: QUANTUM LEAP PACKAGING, INC.
To: INTERPLEXED ENGINEERED PRODUCTS, INC.
Reel/Frame 022892/0082 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 27, 2005
From: SILICON BANDWITH, INC.
To: QUANTUN LEAP PACKAGING, INC.
Reel/Frame 017154/0025 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 1, 2005
From: SILICON BANDWITH, INC.
To: QUANTUM LEAP PACKAGING, INC.
Reel/Frame 016700/0795 →
Continuity (3)
Continuation 0996454200 · Sep 28, 2001
Continuation 0820858600 · Mar 11, 1994
Related Publication 20040140542A1 · Jul 22, 2004