Substrate bias for programming non-volatile memory
View Patent ↗A method and system for substrate bias for programming non-volatile memory. A bias voltage is applied to a deep well structure under a well comprising a channel region for a non-volatile memory cell. During programming, a negative bias applied to the deep well beneficially creates a non-uniform distribution of electrons within the channel region, with an abundance of electrons at the surface of the channel region. The application of additional bias voltages to a control gate and a drain may cause electrons to migrate from the channel region to a storage layer of the non-volatile memory cell. Advantageously, due to the increased supply of electrons at the surface of the channel region, programming of the non-volatile cell takes place faster than under the conventional art.
1. A method of programming a non-volatile memory cell comprising:
applying a first bias voltage to a source, a positive second bias voltage to a drain and a positive third bias voltage to a control gate of said memory cell to program said memory cell; and
applying a negative fourth bias voltage to a deep well region of said memory cell, wherein said deep well region is substantially under a channel region of said memory cell, and wherein said deep well region comprises a dominant charge carrier of a different type than said channel region.
2. The method as described in claim 1 wherein said channel region comprises P-type material and wherein said well region comprises N-type material.
3. The method as described in claim 1 wherein said method further comprises grounding said channel region.
4. The method as described in claim 1 wherein said first bias voltage is substantially ground.
5. The method as described in claim 1 wherein said third bias voltage is greater than said second bias voltage.
6. The method as described in claim 1 wherein said memory cell comprises a floating gate as a storage element.
7. The method as described in claim 1 wherein said memory cell comprises a nitride layer as a storage element.
8. The method as described in claim 1 wherein said memory cell stores more than one bit of information.
9. A method of programming a non-volatile memory cell comprising:
applying a negative bias voltage to a deep well region of said memory cell to inject electrons into a channel region of said memory cell, wherein said deep well region is substantially under said channel region of said memory cell, and wherein said deep well comprises a dominant charge carrier of a different type than said channel region; and
biasing a drain and a control gate of said memory cell to cause electrons to migrate from said channel region to an electrically isolated storage layer of said memory cell.
10. The method of programming a non-volatile memory cell as described in claim 9 further comprising biasing a source of said memory cell.
11. The method of programming a non-volatile memory cell as described in claim 9 further comprising biasing a channel region of said memory cell.
12. The method of programming a non-volatile memory cell as described in claim 9 wherein said electrically isolated storage layer of said memory cell comprises conductive material.
13. The method of programming a non-volatile memory cell as described in claim 9 wherein said electrically isolated storage layer of said memory cell comprises nitride.