Method for exposing a substrate with a structure pattern which compensates for the optical proximity effect
View Patent ↗In a circuit layout, a partial area is defined in a first structure pattern, which is stored electronically in a data format and represents a first lithographic plane, in which partial area a lower limit value for the length of a serif to be added to a structure element in an OPC correction can be undershot in order to locally increase the resolution. The partial area in the electronically stored circuit layout maybe, for example, an active region with which contact is to be made and which has been selected in a second structure pattern of a further lithographic plane as a structure element. Thus, within such a partial area of an integrated circuit, elevated requirements made of dimensionally accurate imaging are satisfied, while the required data volume overall increases only to an insignificant extent.
1. A method for exposing a substrate with correction of the optical proximity effect, comprising:
providing a circuit layout representing an integrated circuit to be formed on the substrate;
creating a first and at least one second structure pattern in the circuit layout, which in each case have an assignment of structure elements to positions within a common idealized basic area;
electronically storing the first and at least the second structure pattern in a data format;
prescribing a lower limit value for a length of a serif, the serif to be added to a segment of an outer side of one of the structure elements in the electronically stored first structure pattern to compensate for the optical proximity effect;
defining a partial area of the idealized basic area, the idealized basic area including at least one selected structure element of the second structure pattern ( 100 ) stored electronically in the data format;
selecting a segment of an outer side of at least one first structure element of the first structure pattern stored electronically in the data format, the segment having a position within the idealized basic area;
comparing the position of the segment in the electronically stored first structure pattern with the partial area;
determining a length of a serif dependent on the comparison result so that the length is less than the lower limit value;
adding the serif to the segment of the outer side of the first structure element in the data format to form a first structure pattern which compensates for the optical proximity effect;
exposing a mask with the compensated first structure pattern; and
transferring and exposing the first structure pattern from the mask to the substrate with correction of the optical proximity effect.
2. The method as claimed in claim 1 , wherein adding the serif to the segment of the outer side of the first structure element is preceded by:
determining an image of the first structure pattern stored electronically in the data format, the image being produced in the case of exposure under the influence of the optical proximity effect on the substrate;
comparing the image with the first structure pattern to be formed, which is stored electronically in the data format; and
determining the length of the serif to be added dependent on the result of the comparison.
3. The method as claimed in claim 1 , wherein the compensated first structure pattern transferred to the substrate after exposing the mask and the substrate and, in the case of a further exposure, the second structure pattern transferred to the substrate represent electrically conductive structure elements in each case in different planes of the integrated circuit.
4. The method as claimed in claim 1 , wherein the first structure element of the first structure pattern, which is transferred to the substrate, represents an interconnect for connecting a number of transistors, the selected second structure element of the second structure pattern to be formed on the substrate represents an active region in which the transistor is to be fabricated.
5. The method as claimed in claim 1 , a further lower limit value is prescribed for the length of the serif, the serif being added to the electronically stored first structure element within the partial area to compensate for the optical proximity effect, which the further lower limit value is less than the prescribed first lower limit value.
6. The method as claimed in claim 5 , wherein the first and the second structure pattern are stored electronically in a data format, in which the position of the structure elements is specified at grid points in a first coordinate grid having a first grid size between adjacent grid lines, the prescribed lower limit value is equal to the first grid size, the definition of the partial area is followed by the setting up of a second coordinate grid having a second grid size, which is reduced compared with the first grid size, within the partial area, the prescribed lower limit value is equal to the second, reduced grid size.