IP Library Granted Patent US 7,064,046
Granted Patent B2
US 7,064,046 · App. 10/771,497 · Granted Jun 20, 2006

Manufacturing method of semiconductor device

Assignees: Sanyo Electric Co., Ltd.; Kanto Sanyo Semiconductors Co., Ltd.
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Quick Facts
Patent No.
US 7,064,046
App. No.
10/771,497
Granted
Jun 20, 2006
Kind
B2
Abstract

The invention provides an algorithm for aligning a rotating blade in a dicing process of partially dicing a wafer attached to a substrate. A width of a cut groove and distance between pads in the cut groove are detected by a recognition camera. Based on a result of this detection, alignment data Δy which is distance between a centerline of the width of the cut groove and a real centerline are calculated. Based on a difference between the distance of the pads in the cut groove and a target value of the distance, data Δz on alignment in a depth direction of the cut groove is calculated. The rotating blade is aligned by using the alignment data Δy and Δz.

Claims (35)

1. A method of manufacturing a semiconductor device, comprising:

providing a wafer comprising a predetermined dicing line region and a pair of pads that are formed on a front surface of the wafer so that part of each of the pads is disposed in the dicing line region;

attaching a first substrate to the front surface of the wafer;

attaching a second substrate to a back surface of the wafer;

forming a cut groove from a surface of the second substrate by moving a blade along the dicing line region so as to expose an end portion of each of the pads in the cut groove;

irradiating the cut groove with detection light;

measuring a width of the cut groove by detecting light reflected from opposing upper end portions of the cut groove;

measuring a distance between the two pads by detecting light reflected from the exposed end portions of the two pads; and

aligning the blade based on a result of the measuring of the width, the distance or both the width and the distance so that a center line of the cut groove is located at a center line of the predetermined dicing line region and that a depth of the cut groove is a predetermined depth.

2. The method of claim 1 , wherein the blade is aligned in a horizontal direction based on a distance between the centerline of the cut groove and the centerline of the dicing line region.

3. The method of claim 1 , wherein the blade is aligned in a vertical direction based on the distance between the two pads.

4. The method of claim 1 , wherein the light reflected from the opposing upper end portions of the cut groove or from the exposed end portions of the two pads is detected by a recognition camera.

5. A method of manufacturing a semiconductor device, comprising:

providing a wafer comprising a predetermined dicing line region and a pad that is formed on a front surface of the wafer so that part of the pad is disposed in the dicing line region;

attaching a first substrate to the front surface of the wafer;

attaching a second substrate to a back surface of the wafer;

forming a cut groove from a surface of the second substrate by moving a blade along the dicing line region so as to expose an end portion of the pad in the cut groove;

irradiating the cut groove with detection light;

determining a position of a centerline of the cut groove by detecting light reflected from opposing upper end portions of the cut groove;

determining a distance between the centerline of the cut groove and the pad by detecting light reflected from the exposed end portion of the pad and by using the determined position of the centerline of the cut groove; and

aligning the blade based on a result of the determining of the position, the distance or both the position and the distance so that the center line of the cut groove is located at a center line of the predetermined dicing line region and that a depth of the cut groove is a predetermined depth.

6. The method of claim 5 , wherein the blade is aligned in a horizontal direction based on a distance between the centerline of the cut groove and the centerline of the dicing line region.

7. The method of claim 5 , wherein the blade is aligned in a vertical direction based on the distance between the centerline of the cut groove and the pad.

8. The method of claim 5 , wherein the light reflected from the opposing upper end portions of the cut groove or from the exposed end portion of the pad is detected by a recognition camera.

9. A method of manufacturing a semiconductor device, comprising:

providing a wafer comprising a predetermined dicing line region and a pad that is formed on a front surface of the wafer so that part of the pad is disposed in the dicing line region;

attaching a substrate to the front surface of the wafer;

forming a cut groove from a back surface of the wafer by moving a blade along the dicing line region so as to expose an end portion of the pad in the cut groove;

irradiating the cut groove with detection light;

determining a position of a centerline of the cut groove by detecting light reflected from opposing upper end portions of the cut groove;

determining a distance between the centerline of the cut groove and the pad by detecting light reflected from the exposed end portion of the pad and by using the determined position of the centerline of the cut groove; and

aligning the blade based on a result of the determining of the position, the distance or both the position and the distance so that the center line of the cut groove is located at a center line of the predetermined dicing line region and that a depth of the cut groove is a predetermined depth.

10. The method of claim 9 , wherein the blade is aligned in a horizontal direction based on a distance between the centerline of the cut groove and the centerline of the dicing line region.

11. The method of claim 9 , wherein the blade is aligned in a vertical direction based on the distance between the centerline of the cut groove and the pad.

12. The method of claim 9 , wherein the light reflected from the opposing upper end portions of the cut groove or from the exposed end portion of the pad is detected by a recognition camera.

Assignments (8)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 22, 2016
From: KANTO SANYO SEMICONDUCTOR CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038988/0665 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 23, 2015
From: WAKUI, MOTOAKI; OCHIAI, ISAO; EYAL, RON; SHETRIT, GIL
To: SANYO ELECTRIC CO., LTD.; KANTO SANYO SEMICONDUCTORS CO., LTD.
Reel/Frame 034802/0029 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT #12/577882 PREVIOUSLY RECORDED ON REEL 026594 FRAME 0385. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2014
From: SANYO ELECTRIC CO., LTD
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 032836/0342 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2011
From: SANYO ELECTRIC CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 026594/0385 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 4, 2004
From: WAKUI, MOTOAKI; OCHIAI, ISAO; EYAL, RON; SHERTRIT, GIL
To: SANYO ELECTRIC CO., LTD.; KANTO SANYO SEMICONDUCTORS CO., LTD.
Reel/Frame 015654/0119 →
Priority Claims (1)
JP 2003-029578 · Feb 6, 2003 · national
Continuity (1)
Related Publication 20050009302A1 · Jan 13, 2005