IP Library Granted Patent US 7,249,231
Granted Patent B2
US 7,249,231 · App. 10/781,974 · Granted Jul 24, 2007

Semiconductor memory with access protection scheme

Assignee: STMicroelectronics S.r.l.
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Quick Facts
Patent No.
US 7,249,231
App. No.
10/781,974
Granted
Jul 24, 2007
Kind
B2
Abstract

A memory, particularly but not limitatively a flash memory, comprises at least one data storage area comprising a plurality of data storage locations, and an access circuitry for accessing the data storage locations for either retrieving or altering a data content thereof, depending for example on a memory user request. The memory includes at least one first user-configurable flag element and a second user-configurable flag element. Both the at least one first and the second flag elements are used by a user to set a protected state of the respective data storage area against alteration of the content of the data storage locations thereof. The protected state defined by setting the first flag element is user-removable, i.e., it can be removed by request from the user, so as to enable again the alteration of the content of the data storage area. On the contrary, the protected state defined by setting the second flag element is permanent and, once set, it cannot be removed: the data storage area becomes unalterable.

Claims (12)

1. A memory comprising:

at least one data storage area comprising a plurality of data storage locations;

an access circuitry for accessing the data storage locations for retrieving or altering a data content thereof; and

at least one first user-configurable flag element and a second user-configurable flag element associated with said storage area, the first and second flag elements being used to define a protected state of the data storage area against alteration of the content of the data storage locations thereof, the protected state defined by the at least one first flag element being user-removable, while the protected state defined by the second flag element being permanent and non-removable,

in which the at least one first flag element has a first state and a second state, in which any alteration of the data content of the respective data storage area is allowed and, respectively, inhibited, and

the second flag element has a first state and a second state, in which changing of the state of the second flag element from the second state to the first state is allowed and, respectively, inhibited, so that when the second flag element is in the second state the respective data storage area is permanently protected against alteration of the data content thereof.

2. The memory of claim 1 , in which said second flag element can be set to define the permanent protected state of the respective data storage area irrespective of the fact that the at least one first flag element is set to define the removable protected state.

3. The memory of claim 1 , in which the at least one first flag element comprises a non-volatile programmable and erasable storage element, and the second flag element comprises a one-time programmable non-volatile storage element.

4. The memory of claim 1 , in which the second flag element can be set into the second state only if the at least one first flag element is in the second state.

5. The memory of claim 1 , in which said at least one storage area comprises at least two storage areas, and in which for each of said at least two storage areas a respective first and second user-configurable flag elements are provided.

6. The memory of claim 1 , comprising at least one further data storage area comprising a plurality of storage locations, and user-configurable flag means associated with said at least one further data storage area adapted to define a protected state of the at least one further data storage area against the alteration of the content of the respective storage locations, said protected state being removable by the user and not permanent.

7. The memory of claim 1 , comprising means for conditioning the configuring of said first and second flag elements by the user on the recognition of the user by the memory.

Assignments (12)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
CORRECTIVE RECORDATION COVERSHEET AND APPENDIX TO REMOVE ERRONEOUSLY LISTED APPLICATION SERIAL NO. 11/495876 ON REEL 029406 FRAME 001 Recorded Dec 11, 2013
From: NUMONYX B.V.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032069/0337 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2013
From: STMICROELECTRONICS S.R.L.
To: STMICROELECTRONICS NV
Reel/Frame 029631/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 21, 2012
From: NUMONYX B.V.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 029406/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 4, 2012
From: STMICROELECTRONICS N.V.
To: NUMONYX B.V.
Reel/Frame 029076/0493 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 4, 2004
From: BABUDRI, IRENE; GHEZZI, STEFANO; GIANNINI, GIUSEPPE; DE LUCA, RUGGERO
To: STMICROELECTRONICS S.R.L.
Reel/Frame 015412/0551 →
Priority Claims (1)
EP 03425093 · Feb 18, 2003 · regional
Continuity (1)
Related Publication 20040205314A1 · Oct 14, 2004