Clock shift circuit for gradual frequency change
View Patent ↗A circuit for changing clocks includes a clock generating circuit which generates an output clock signal by controlling a frequency of an original clock signal, and a control circuit which controls the clock generating circuit in response to an operation mode change signal indicative of a change from a first operation mode to a second operation mode of an external circuit operating based on the output clock signal, thereby changing the output clock signal from a first frequency corresponding to the first operation mode to an intervening frequency and then from the intervening frequency to a second frequency corresponding to the second operation mode, the intervening frequency having a frequency between the first frequency and the third frequency.
1. A circuit for changing clocks, comprising:
a clock generating circuit generating an output clock signal by controlling a frequency of an original clock signal and comprising:
a frequency divider which performs frequency division, and
a decimated clock generating circuit which decimates clock pulses; and
a control circuit controlling said clock generating circuit in response to an operation mode change signal, indicative of a change from a first operation mode to a second operation mode of an external circuit operating based on the output clock signal, thereby changing the output clock signal from a first frequency corresponding to the first operation mode to a third frequency and then from the third frequency to a second frequency corresponding to the second operation mode, the third frequency having a frequency between the first frequency and the second frequency.
2. The circuit as claimed in claim 1 , wherein said control circuit controls said clock generating circuit so as to change the third frequency gradually between the first frequency and the second frequency.
3. The circuit as claimed in claim 1 , wherein:
the frequency divider generates one or more frequency-divided clock signals by dividing the original clock signal;
said clock generating circuit further comprises a selector circuit which selects one of the original clock signal and said one or more frequency-divided clock signals as a selected clock signal;
the decimated clock generating circuit decimates one or more clock pulses of the selected clock signal for outputting as the output clock signal; and
said control circuit controls the selection performed by said selector circuit and the decimation performed by said decimated clock generating circuit in response to the operation mode change signal.
4. The circuit as claimed in claim 3 , wherein said control circuit includes a memory circuit for storing data indicative of a time duration in which the intervening frequency is maintained.
5. The circuit as claimed in claim 4 , wherein each said data stored in said memory circuit corresponds to one of a plurality of different types of the operation mode change signal.
6. The circuit as claimed in claim 3 , wherein said control circuit includes a register for storing a rate of the pulse decimation performed by said decimated clock generating circuit.
7. The circuit as claimed in claim 6 , wherein each said rate stored in said register corresponds to one of a plurality of different types of the operation mode change signal.
8. The circuit as claimed in claim 1 , wherein the operation mode change signal is one of a plurality of types of operation mode change signals, and said control circuit changes the controlling of said clock generating circuit depending on a type of the operation mode change signal.
9. The circuit as claimed in claim 8 , wherein the operation mode change signals include an operation mode change signal indicative of a change to a state in which an operation of the external circuit is suspended and an operation mode change signal indicative of a change to a state in which the operation of the external circuit is restored.