Integrated circuit feature layout for improved chemical mechanical polishing

1. A level of an integrated circuit comprising:

a core area having a 25 μm 2 area, said core area having a first density of features wherein said first density of features is the total area of features in the core area divided by the total core area; and

a peripheral area adjacent to said core area and having a 25 μm 2 area, said peripheral area having a second density of features wherein said second density is the total area of features in the peripheral area divided by the total peripheral area, wherein said second density is substantially similar to said first density.

2. The level of an integrated circuit of claim 1 wherein said second density is within ±10% of said first density.

3. A level of an integrated circuit comprising:

a first area having a first plurality of active features having a first active feature density in a 25 μm 2 area, wherein said first active feature density is the total area of active features in said first area divided by the total area of said first area; and

a second area 25 μm 2 area adjacent to said first area 25 μm 2 area, said second area having a plurality of dummy features having a second feature density in a 25 μm 2 area substantially similar to said first active feature density.

4. The level of claim 3 wherein said first active feature density is approximately 50%.

5. The integrated circuit of claim 3 wherein said dummy features have substantially the same pitch as the active features in said first area.

6. The level of an integrated circuit of claim 3 wherein said dummy features have substantially the same shape and spacing as said active features in said first area.

7. The level of claim 3 wherein said shape and spacing of said dummy features are within 30% of said shape and spacing of said first plurality of features.