IP Library Granted Patent US 7,037,754
Granted Patent B2
US 7,037,754 · App. 10/805,385 · Granted May 2, 2006

Semiconductor chip and method of producing the same

Assignee: Rohm Co., Ltd.
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Quick Facts
Patent No.
US 7,037,754
App. No.
10/805,385
Granted
May 2, 2006
Kind
B2
Abstract

A semiconductor chip which is to be overlapped with and joined to a surface of another solid device. The semiconductor chip has a surface protective film for covering internal wiring, an external connection pad which is formed by partially exposing the internal wiring from the surface protective film, and a wire connecting portion which is formed using a metal material having oxidation resistance on the external connection pad and to which a wire for electrical connection to an external terminal is connected. It is preferable that the semiconductor chip further has an internal connection pad used for connection to the solid device and a bump formed on the pad.

Claims (9)

1. A method of producing a semiconductor chip which is to be overlapped with and joined to a surface of another solid device, comprising the steps of:

stacking a surface protective film on internal wiring;

forming an opening on the surface protective film to partially expose said internal wiring, to form an external connection pad and an internal connection pad; and

selectively plating said external connection pad and the internal connection pad, to respectively form a wire connecting portion to which a wire for electrical connection to an external terminal is connected and a bump for electrical connection to the other solid device.

2. A method of producing a semiconductor device having a chip-on-chip structure in which a secondary chip is overlapped with and joined to a surface of a primary chip, comprising the steps of:

stacking a surface protective film on internal wiring in the primary chip;

forming an opening on said surface protective film to partially expose said internal wiring, to form an external connection and an internal connection;

and selectively plating said external connection pad and the internal connection pad, to respectively form a wire connecting portion to which a wire for electrical connection to an external terminal is connected and a bump for electrical connection to said secondary chip; and

joining the primary chip and the secondary chip to each other through said bump.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 17, 2020
From: ACHLYS TECHNOLOGIES INC.
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 052957/0699 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 31, 2020
From: ROHM CO., LTD.
To: ACHLYS TECHNOLOGIES INC.
Reel/Frame 052273/0877 →
Priority Claims (1)
JP 11-265744 · Sep 20, 1999 · national
Continuity (2)
Division 0966566300 · Sep 20, 2000
Related Publication 20040173917A1 · Sep 9, 2004