Broken symmetry for optimization of resource fabric in a sea-of-platform architecture
View Patent ↗The present invention is directed to a method and system for optimally mapping a general set of resources to a specific integrated circuit design. In an exemplary aspect of the present invention, a method for optimally mapping a general set of resources to a specific integrated circuit design may include the following steps. Sets of transistors are first abstracted into abstracted resources. The abstracted resources may include a transformative resource, a coordinating resource, and a state management resource, and the like. Then, a sea-of-platforms is utilized for unifying a flexible and malleable collection of the abstracted resources in such a way as to optimize the abstracted resources for a specific integrated circuit design. Broken symmetry may be used to optimize the abstracted resources for the specific integrated circuit design. The broken symmetry may be in at least one of a physical 3 -dimensional space, a temporal space and a code space.
1. A method for optimally mapping a general set of resources to a specific integrated circuit design, comprising steps of:
abstracting sets of transistors into abstracted resources, said abstracted resources including at least one of a transformative resource, a coordinating resource, and a state management resource; and
utilizing a sea-of-platforms for unifying a collection of said abstracted resources in such a way as to optimize said abstracted resources for a specific integrated circuit design, said abstracted resources configured for being fashioned into multiple arrangements,
wherein said utilizing step comprises implementing a plesiochronous signaling discipline in said sea-of-platforms, said plesiochronous signaling discipline providing just necessary timing resources for achieving a particular task, the particular task being at least one of decoding, de-serialization, and filtering.
2. The method of claim 1 , wherein said transformative resource includes at least one of conversion and translation of data, modulation, calculation, and coding and decoding.
3. The method of claim 1 , wherein said coordinating resource includes at least one of timing, synchronization, buffering, and caching.
4. The method of claim 1 , wherein said state management resource includes at least one of control of non-volatile storage structures, and tree traversal capabilities.
5. The method of claim 1 , wherein said utilizing step comprises using broken symmetry to optimize said abstracted resources for said specific integrated circuit design.
6. The method of claim 5 , wherein said broken symmetry is in at least one of a physical 3-dimensional space, a temporal space and a code space.
7. A system for optimally mapping a general set of resources to a specific integrated circuit design, comprising:
means for abstracting sets of transistors into abstracted resources, said abstracted resources including at least one of a transformative resource, a coordinating resource, and a state management resource; and
means for utilizing a sea-of-platforms for unifying a collection of said abstracted resources in such a way as to optimize said abstracted resources for a specific integrated circuit design, said abstracted resources configured for being fashioned into multiple arrangements,
wherein said utilizing means comprises means for implementing a plesiochronous signaling discipline in said sea-of-platforms, said plesiochronous signaling discipline providing just necessary timing resources for achieving a particular task, the particular task being at least one of decoding, de-serialization, and filtering.
8. The system of claim 7 , wherein said transformative resource includes at least one of conversion and translation of data, modulation, calculation, and coding and decoding.
9. The system of claim 7 , wherein said coordinating resource includes at least one of timing, synchronization, buffering, and caching.
10. The system of claim 7 , wherein said state management resource includes at least one of control of non-volatile storage structures, and tree traversal capabilities.
11. The system of claim 7 , wherein said utilizing step comprises means for using broken symmetry to optimize said abstracted resources for said specific integrated circuit design.
12. The system of claim 11 , wherein said broken symmetry is in at least one of a physical 3-dimensional space, a temporal space and a code space.
13. A computer-readable medium having computer-executable instructions for performing a method for optimally mapping a general set of resources to a specific integrated circuit design, said method comprising steps of:
abstracting sets of transistors into abstracted resources, said abstracted resources including at least one of a transformative resource, a coordinating resource, and a state management resource; and
utilizing a sea-of-platforms for unifying a collection of said abstracted resources in such a way as to optimize said abstracted resources for a specific integrated circuit design, said abstracted resources configured for being fashioned into multiple arrangements,
wherein said utilizing step comprises implementing a plesiochronous signaling discipline in said sea-of-platforms, said plesiochronous signaling discipline providing just necessary timing resources for achieving a particular task, the particular task being at least one of decoding, de-serialization, and filtering.
14. The computer-readable medium of claim 13 , wherein said transformative resource includes at least one of conversion and translation of data, modulation, calculation, and coding and decoding.
15. The computer-readable medium of claim 13 , wherein said coordinating resource includes at least one of timing, synchronization, buffering, and caching.
16. The computer-readable medium of claim 13 ,
wherein said state management resource includes at least one of control of non-volatile storage structures, and tree traversal capabilities.
17. The computer-readable medium of claim 13 , wherein said utilizing step comprises using broken symmetry to optimize said abstracted resources for said specific integrated circuit design.
18. The computer-readable medium of claim 17 , wherein said broken symmetry is in at least one of a physical 3-dimensional space, a temporal space and a code space.