Full-swing wordline driving circuit
View Patent ↗A circuit is proposed for driving a memory line controlling at least one memory cell of a non-volatile memory device, the circuit being responsive to a first and a second selection signals, each one suitable to assume a first logic value or a second logic value, wherein the circuit includes a first level shifter for converting the first selection signal into a first operative signal and a second level shifter for converting the second selection signal into a second operative signal, each level shifter including first shifting means for shifting one of the logic values of the corresponding selection signal to a first bias voltage, and a selector for applying the first operative signal or a second bias voltage to the memory line according to the second operative signal; in the circuit of the invention each level shifter further includes second shifting means for shifting another of the logic values of the corresponding selection signal to the second bias voltage.
1. A circuit for driving a memory line controlling at least one memory cell of a non-volatile memory device, the circuit being responsive to a first and a second selection signals each one suitable to assume a first logic value or a second logic value, wherein the circuit comprises:
a first level shifter for converting the first selection signal into a first operative signal and a second level shifter for converting the second selection signal into a second operative signal, each level shifter including first shifting means for shifting one of the logic values of the corresponding selection signal to a first bias voltage;
a selector for applying the first operative signal or a second bias voltage to the memory line according to the second operative signal; and
each level shifter further includes second shifting means for shifting another of the logic values of the corresponding selection signal to the second bias voltage.
2. The circuit according to claim 1 wherein the selector includes a first electronic switch for applying the first operative signal to the memory line and a second electronic switch for applying the second bias voltage to the memory line, the first and the second electronic switches being controlled by the second operative signal.
3. The circuit according to claim 1 wherein each level shifter includes a first stage for converting the selection signal into an intermediate signal through the first shifting means, the first stage having a first leg for providing the intermediate signal and a further first leg for providing a further intermediate signal opposite to the intermediate signal, and a second stage for converting the intermediate signal into the operative signal, the second stage having a second leg for providing the operative signal and a further second leg for providing a further operative signal opposite to the operative signal, and wherein the selector includes a further electronic switch for applying the second bias voltage to the memory line, the further electronic switch being controlled by the further operative signal provided by the first level shifter.
4. The circuit according to claim 1 wherein each level shifter includes latching means for latching the operative signal, the latching means being supplied by the first and the second bias voltages, and means for setting the latching means according to the selection signal, the means for setting being disabled when the first bias voltage is equal to the first logic value or the second logic value.
5. The circuit according to claim 4 wherein the latching means includes a first inverter having a first input terminal and a first output terminal and a second inverter having a second input terminal, connected to the first output terminal, and a second output terminal, connected to the first input terminal, the first output terminal providing the operative signal and the second output terminal providing the further operative signal, and wherein the means for setting includes a first transistor for applying the first bias voltage to the first input terminal in response to the intermediate signal and a second transistor for applying the first bias voltage to the second input terminal in response to the further intermediate signal.
6. The circuit according to claim 1 wherein the memory line is a wordline.
7. A non-volatile memory device, comprising:
a plurality of memory cells;
a plurality of memory lines each one controlling at least one of the memory cells;
means for decoding a memory line address into a plurality of first selection signals and a plurality of second selection signals; and
a plurality of circuits for driving the memory lines, the circuits being responsive to first and a second selection signals each one suitable to assume a first logic value or a second logic value, each circuit including:
a first level shifter to convert the first selection signal into a first operative signal and a second level shifter to convert the second selection signal into a second operative signal, each level shifter including a first shifting element to shift one of the logic values of the corresponding selection signal to a first bias voltage;
a selector to apply the first operative signal or a second bias voltage to a memory line according to the second operative signal; and
each level shifter further including a second shifting element to shift another of the logic values of the corresponding selection signal to the second bias voltage, wherein the selectors are each for a corresponding memory line, the selectors being grouped into a plurality of sets, the first level shifters are each to provide the first operative signal to a corresponding selector in all the sets, and the second level shifters are each to provide the second operative signal to all the selectors in a corresponding set.
8. The memory device according to claim 7 wherein the memory device is of the flash type.
9. A method of driving a memory line controlling at least one memory cell of a non-volatile memory device, the method comprising:
providing a first and a second selection signals, each one suitable to assume a first logic value or a second logic value;
converting the first selection signal into a first operative signal and the second selection signal into a second operative signal by shifting one of the logic values of the corresponding selection signal to a first bias voltage;
applying the first operative signal or a second bias voltage to the memory line according to the second operative signal; and
said converting further includes shifting another of the logic values of the corresponding selection signal to the second bias voltage.
10. A method of erasing a flash memory including a plurality of wordlines each one associated with a first and a second selection signals, each one suitable to assume a first logic value or a second logic value, the method comprising:
selecting at least one wordline by asserting the corresponding first and second selection signals,
converting each first selection signal into a first operative signal and each second selection signal into a second operative signal by shifting one of the logic values of the corresponding selection signal to a first bias voltage and another of the logic values of the corresponding selection signal to a second bias voltage,
latching each operative signal by corresponding latching means, the latching means being supplied by the first and the second bias voltages,
setting the first bias voltage to the first logic value and the second bias voltage to an erase value, and
applying the second bias voltage to each selected wordline and the corresponding first operative signal to each non-selected wordline in response to the corresponding second operative signal.
11. A circuit to drive a memory line that controls at least one memory cell of a non-volatile memory device, the circuit being responsive to first and second selection signals that are suitable to assume a first logic value or a second logic value, the circuit comprising:
a first level shifter to convert the first selection signal into a first operative signal and a second level shifter to convert the second selection signal into a second operative signal, each level shifter including a first shifting element to shift one of the logic values of the corresponding selection signal to a first bias voltage; and
a selector to apply the first operative signal or a second bias voltage to the memory line according to the second operative signal, wherein each level shifter further includes:
a second shifting element to shift another of the logic values of the corresponding selection signal to the second bias voltage;
a latching element to latch the operative signal, the latching element being supplied by the first and the second bias voltages; and
a setting element to set the latching element according to the selection signal, the setting element being disabled when the first bias voltage is equal to the first logic value or the second logic value.
12. The circuit of claim 11 wherein the memory device is a flash type memory device.
13. A circuit to drive a memory line that controls at least one memory cell of a non-volatile memory device, the circuit being responsive to first and second selection signals that are suitable to assume a first logic value or a second logic value, the circuit comprising:
a first level shifter to convert the first selection signal into a first operative signal and a second level shifter to convert the second selection signal into a second operative signal, each level shifter including a first shifting element to shift one of the logic values of the corresponding selection signal to a first bias voltage; and
a selector to apply the first operative signal or a second bias voltage to the memory line according to the second operative signal, wherein each level shifter further includes:
a second shifting element to shift another of the logic values of the corresponding selection signal to the second bias voltage;
a first stage to convert the selection signal into an intermediate signal through the first shifting element, the first stage having a first leg to provide the intermediate signal and a further first leg to provide a further intermediate signal opposite to the intermediate signal; and
a second stage to convert the intermediate signal into the operative signal, the second stage having a second leg to provide the operative signal and a further second leg to provide a further operative signal opposite to the operative signal, and wherein the selector includes a further electronic switch to apply the second bias voltage to the memory line, the further electronic switch being controllable by the further operative signal provided by the first level shifter.
14. The circuit of claim 13 wherein the memory device is a flash type memory device.