Flip chip interconnection structure
View Patent ↗A flip chip interconnection structure is formed by mechanically interlocking joining surfaces of a first and second element. The first element, which may be a bump on an integrated circuit chip, includes a soft, deformable material with a low yield strength and high elongation to failure. The surface of the second element, which may for example be a substrate pad, is provided with asperities into which the first element deforms plastically under pressure to form the mechanical interlock.
1. A flip chip semiconductor device, comprising:
a semiconductor die having first interconnect members with substantially linear sidewalls and made with a deformable material; and
a substrate having second interconnect members, the second interconnect members each having a plated surface with a plurality of asperities extending 1-25 micrometers from the plated surface, the first and second interconnect members being respectively permanently bonded together by compressing the first and second interconnect members to cause plastic flow of the first interconnect members into the asperities of the second interconnect members to electrically interconnect the semiconductor die and substrate, the first interconnect members undergoing plastic deformation of at least 25 micrometers to incorporate the asperities of the second interconnect members into the deformable material of the first interconnect members while maintaining the substantially linear sidewalls of the first interconnect members to reduce pitch between adjacent first interconnect members.
2. The flip chip semiconductor device of claim 1 , wherein the first interconnect members each include a bump formed on the semiconductor die.
3. The flip chip semiconductor device of claim 1 , wherein the deformable material of the first interconnect members is selected from the group consisting of gold, copper, and nickel.
4. The flip chip semiconductor device of claim 1 , wherein the second interconnect members each include an interconnect pad.
5. The flip chip semiconductor device of claim 1 , wherein the second interconnect members include lead.
6. The flip chip semiconductor device of claim 1 , wherein the plastic deformation occurs along a sidewall of the first interconnect members.
7. A flip chip semiconductor device, comprising:
a semiconductor die having a plurality of bumps with substantially linear sidewalls and made with a deformable material; and
a substrate having a plurality of interconnect pads, the interconnect pads each having a plated surface with a plurality of asperities extending from the plated surface to form an irregular surface, the bumps and interconnect pads being permanently bonded together by applying a compressive force to the bumps and interconnect pads to cause plastic flow of the bumps into the asperities of the interconnect pads to form an electrical interconnection between the semiconductor die and the substrate, the bumps undergoing plastic deformation to incorporate the asperities of the interconnect pads into the deformable material of the bumps while maintaining the substantially linear sidewalls of the bumps to reduce pitch between adjacent bumps and to permanently resist breaking the electrical interconnection after the compressive force is removed.
8. The flip chip semiconductor device of claim 7 , wherein the plurality of asperities each extend 1-25 micrometers from the plated surface of the interconnect pads.
9. The flip chip semiconductor device of claim 7 , wherein the bumps undergo a plastic deformation of at least 25 micrometers.
10. The flip chip semiconductor device of claim 7 , wherein the plastic deformation occurs along a sidewall of the bumps.
11. The flip chip semiconductor device of claim 7 , wherein the deformable material of the bumps is made with a material selected from the group consisting of gold, copper, and nickel.
12. A semiconductor device, comprising:
a semiconductor die having a plurality of bumps made with a deformable material; and
a substrate having a plurality of interconnect pads, the interconnect pads each having a plated surface with a plurality of asperities extending from the plated surface to form an irregular surface, the bumps and interconnect pads being permanently bonded together by applying a compressive force to the bumps and the interconnect pads to cause a plastic flow of the bumps into the asperities of the interconnect pads to form an electrical interconnection between the semiconductor die and the substrate, the bumps undergoing plastic deformation to incorporate the asperities of the interconnect pads into the deformable material of the bumps and to permanently resist breaking the electrical interconnection after the compressive force is removed.
13. The semiconductor device of claim 12 , wherein the bumps have substantially linear sidewalls.
14. The semiconductor device of claim 13 , wherein the bumps maintain the substantially linear sidewalls during the plastic deformation to reduce pitch between adjacent bumps.
15. The semiconductor device of claim 12 , wherein the deformable material of the bumps is made with a material selected from the group consisting of gold, copper, and nickel.
16. The semiconductor device of claim 12 , wherein the plastic deformation occurs along a sidewall of the bumps.
17. The semiconductor device of claim 12 , wherein the plurality of asperities each extend 1-25 micrometers from the plated surface of the interconnect pads.
18. The semiconductor device of claim 12 , wherein the bumps undergo a plastic deformation of at least 25 micrometers.
19. A semiconductor device, comprising:
a semiconductor die;
a plurality of bumps disposed on the die, the bumps comprising a deformable material, each of the bumps further comprising a deformed portion disposed at a distal end of the bump, the deformed portion characterized as an area of plastic flow of the deformable material formed when a compressive force was applied to the bumps;
a substrate; and
a plurality of interconnect pads disposed on the substrate, the interconnect pads having a plurality of asperities, the deformed portions of the bumps abutting and filling recesses between the asperities to permanently interlock the bumps to the interconnect pads and to form an electrical interconnection between the semiconductor die and substrate such that the electrical interconnection is permanently maintained in an absence of the compressive force.
20. The semiconductor device of claim 19 , wherein the bumps have substantially linear sidewalls.
21. The semiconductor device of claim 20 , wherein the bumps undergoing plastic deformation to incorporate the asperities of the interconnect pads into the deformable material of the bumps while maintaining the substantially linear sidewalls to reduce pitch between adjacent bumps.