Mask set having separate masks to form different regions of integrated circuit chips, exposure system including the mask set with an aperture device, and method of using the mask set to expose a semiconductor wafer
View Patent ↗A mask set for the production of integrated circuit chips, wherein a first mask has first features that form inner cell regions and a second mask has second features that form outer non-cell regions, so that the first and second masks do no expose a same region of a semiconductor wafer. An exposure system includes the mask set with an aperture device to fade out partial regions of the first features during exposure of the wafer by a light source. Furthermore, the mask set is used in a method of exposing a wafer for producing integrated circuit chips.
1. A mask set for the production of integrated circuit chips, the mask set comprising:
a first mask comprising a plurality of first features for forming inner cell regions of the integrated circuit chips; and
a second mask comprising a plurality of second features for forming outer non-cell regions of the integrated circuit chips, wherein the first mask and the second mask do not expose a same region of a wafer.
2. The mask set according to claim 1 , wherein the integrated circuit chips comprise memory chips.
3. The mask set according to claim 2 , wherein the plurality of first features serves for the exposure of regions of the memory chips on which memory cells of the memory chips are produced.
4. The mask set according to claim 1 , wherein the plurality of first features is a structure homogeneously recurring in a longitudinal and/or a transverse direction of the first mask.
5. The mask set according to claim 1 , wherein the plurality of first features is a line structure.
6. The mask set according to claim 1 , wherein the inner cell regions comprise a line structure with continuous lines.
7. The mask set according to claim 1 , wherein the plurality of first features form a region on the first mask, wherein the region extends over an entire face of the first mask, except an edge region on the first mask.
8. The mask set according to claim 7 , wherein the edge region comprises an alignment structure and/or a barcode structure and/or a structureless frame region.
9. The mask set according to claim 1 , wherein the plurality of first features form a region on the first mask, the region extends over an entire face of the mask.
10. The mask set according to claim 1 , wherein the first mask comprises a mask type selected from the group comprising a photo mask, non-optical mask, ultraviolet mask, and Ion Projection Lithography mask.
11. The mask set according to claim 1 , wherein the second mask comprises a mask type selected from the group comprising a photo mask, non-optical mask, ultraviolet mask, and Ion Projection Lithography mask.
12. The mask set of claim 1 , wherein the plurality of second features form regions for connecting logic devices, pad logic devices, connecting lines, spines or kerfs.
13. The mask set of claim 1 , wherein the first mask and second mask are exposed together to form composite patterns.
14. The mask set of claim 1 , further comprising an aperture device comprising a non-transparent fadeout region for fading out at least a part of the first features of the first mask.
15. The mask set of claim 14 , wherein the aperture device fades out first features over the non-cell regions.
16. An exposure system using the mask set of claim 1 , the exposure system comprising:
a light source disposed above a wafer holder, wherein the first mask is disposed between the light source and the wafer holder; and
an aperture device comprising a plurality of third features disposed between the light source and the wafer holder, wherein the plurality of third features fade out a part of the plurality of first features from exposing.
17. The exposure system of claim 16 , wherein the faded out regions form non-cell regions of an integrated circuit chip.
18. The exposure system of claim 17 , wherein a region, excluding the faded out regions, forms cell regions of the integrated circuit chip.
19. The exposure system of claim 16 , wherein the plurality of first features is a structure homogeneously recurring in a longitudinal and/or a transverse direction of the mask.
20. The exposure system of claim 19 , wherein the structure comprises lines.
21. A method for the production of integrated circuit chips comprising exposing a wafer using the mask set of claim 1 .
22. The method according to claim 21 , further comprising fading out partial regions of the first mask during exposure of the wafer.
23. The method according to claim 22 , wherein a separate aperture device is used for fading out the partial regions.
24. The method according to claim 23 , wherein the faded out regions are exposed by making use of the second mask.
25. A mask set for the production of integrated circuit chips, comprising a first mask and a second mask, the first mask comprising a plurality of first features for forming structured outer non-cell regions of the integrated circuit chips, the second mask comprising a plurality of second features for forming inner cell regions of the integrated circuit chips, wherein the first mask and the second mask do not expose a same region when aligned over a wafer.
26. The mask set of claim 25 , wherein the structured outer non-cell regions are identical.
27. The mask set of claim 26 , wherein the identical structured outer non-cell regions are selected from the group comprising connecting logic devices, pad logic devices, connecting lines, spines, or kerfs.
28. The mask set of claim 25 , wherein the inner cell regions comprise memory cell arrays.
29. A mask set for the production of integrated circuit chips, the mask set comprising:
a first mask comprising a layout structure; and
an aperture device comprising a non-transparent fadeout region for fading out at least a part of the layout structure of the first mask, wherein the first mask and the aperture device are exposed simultaneously in an exposure system.