Memory device for storing electrical charge and method for fabricating the same

1. A memory device for storing electrical charges, comprising:

a substrate;

at least two doping regions embedded in the substrate;

at least one gate dielectric for connecting two adjacent doping regions;

at least one word line applied on the at least one gate dielectric;

a node contact-making element for connecting the word line to a barrier layer;

an electrode layer deposited on the barrier layer;

tube elements applied on the electrode layer and contact-connected thereto;

a dielectric coating, with which the tube elements are coated;

a filling material for filling the space between the tube elements; and

a counter-electrode, which is connected to the filling material and is arranged such that an electrical capacitor for storing electrical charge is formed between the electrode layer and the counter-electrode.

2. The device according to claim 1 , wherein the substrate is formed from a p-conducting silicon material.

3. The device according to claim 1 , wherein the doping regions embedded in the substrate are formed as highly doped n-conducting regions.

4. The device according to claim 3 , wherein the doping of the doping regions embedded in the substrate is more than 10 20 cm −3 .

5. The device according to claim 1 , wherein the doping regions embedded in the substrate are provided as drain and source regions of the memory device.

6. The device according to claim 1 , wherein the node contact-making element for connecting the word line to the barrier layer is formed from polysilicon.

7. The device according to claim 1 , wherein the node contact-making element for connecting the word line to the barrier layer is formed from tungsten.

8. The device according to claim 1 , wherein the barrier layer is formed from an electrically conductive material.

9. The device according to claim 1 , wherein the electrode layer deposited on the barrier layer is formed from aluminum.

10. The device according to claim 1 , wherein the tube elements applied on the electrode layer and contact-connected thereto are carbon nanotubes.

11. The device according to claim 10 , wherein the carbon nanotubes applied on the electrode layer and contact-connected thereto are provided by growth nuclei comprising ink.

12. The device according to claim 11 , wherein the carbon nanotubes applied on the electrode layer and contact-connected thereto are formed from growth nuclei of Fe(NO 3 )3*9H 2 O ink.

13. The device according to claim 1 , wherein the tube elements are coated with a metallization layer.

14. The device according to claim 1 , wherein the filling material for filling the space between the tube elements is an electrically conductive material.

15. The device according to claim 14 , wherein the filling material for filling the space between the tube elements comprises polysilicon or a titanium nitride.

16. The device according to claim 1 , wherein the dielectric coating with which the tube elements are coated comprises a material having a high relative permittivity.

17. The device according to claim 1 , wherein the dielectric coating with which the tube elements are coated comprises aluminum oxide.

18. The device according to claim 1 , wherein the counter-electrode connected to the filling material is at ground potential.

19. The device according to claim 1 , wherein the tube elements applied on the electrode layer and contact-connected thereto have an axis of symmetry that is perpendicular to the electrode layer.

20. A method for fabricating a memory device for storing electrical charges, comprising:

providing a substrate;

embedding at least two doping regions in the substrate;

applying at least one gate dielectric for connecting two adjacent doping regions;

applying at least one word line on the at least one gate dielectric;

providing a node contact-making element for connecting the word line to a barrier layer;

depositing an electrode layer on the barrier layer;

applying and contact-connecting tube elements on the electrode layer;

coating the tube elements with a dielectric coating;

filling the space between the tube elements with a filling material; and

connecting a counter-electrode to the filling material such that an electrical capacitor for storing electrical charge is formed between the electrode layer and the counter-electrode.

21. The method according to claim 20 , wherein the substrate is provided from a p-conducting silicon material.

22. The method according to claim 20 , wherein the doping regions embedded in the substrate are formed as highly doped n-conducting regions.

23. The device according to claim 3 , wherein the doping of the doping regions embedded in the substrate is set to more than 10 20 cm −3 .

24. The method according to claim 20 , wherein the doping regions embedded in the substrate are provided as drain and source regions of the memory device.

25. The method according to claim 20 , wherein the node contact-making element for connecting the word line to the barrier layer is embodied from polysilicon.

26. The method according to claim 20 , wherein the node contact-making element for connecting the word line to the barrier layer is embodied from tungsten.

27. The method according to claim 20 , wherein the barrier layer is formed from an electrically conductive material.

28. The method according to claim 20 , wherein the electrode layer deposited on the barrier layer is formed from aluminum.

29. The method according to claim 20 , wherein the tube elements applied on the electrode layer and contact-connected thereto are provided as carbon nanotubes.

30. The method according to claim 20 , wherein the carbon nanotubes applied on the electrode layer and contact-connected thereto are provided by growth nuclei comprising ink.

31. The method according to claim 20 , wherein the carbon nanotubes applied on the electrode layer and contact-connected thereto are formed from growth nuclei of Fe(NO 3 )3*9H 2 O ink.

32. The method according to claim 20 , wherein the tube elements are coated with a metallization layer.

33. The method according to claim 20 , wherein growth nuclei for the carbon nanotubes that are to be applied on the electrode layer and contact-connected thereto are applied by a stamp device.

34. The method according to claim 33 , wherein the stamp device is provided as a plastic stamp made of polydimethylsiloxane.

35. The method according to claim 33 , wherein a stamp structure of the stamp device is provided by electron beam lithography.

36. The method according to claim 20 , wherein the filling material for filling the space between the tube elements is formed by an electrically conductive material.

37. The method according to claim 36 , wherein the filling material for filling the space between the tube element is provided from polysilicon.

38. The method according to claim 20 , wherein the dielectric coating with which the tube elements are coated is formed from a material having a high relative permittivity.

39. The method according to claim 20 , wherein the dielectric coating with which the tube elements are coated is provided from aluminum oxide.

40. The method according to claim 20 , wherein the counter-electrode connected to the filling material is put at ground potential.

41. The method according to claim 20 , wherein the tube elements applied on the electrode layer and contact-connected thereto are oriented such that they have an axis of symmetry that is perpendicular to the electrode layer.

42. The method according to claim 20 , wherein the carbon nanotubes that are formed from growth nuclei and are to be applied on the electrode layer and contact-connected thereto are deposited by a chemical vapor deposition method.

43. The method according to claim 36 , wherein the electrically conductive material from which the filling material for filling the space between the tube elements is formed is provided by a titanium nitride.