Semiconductor device formed having a metal layer for conducting the device current and for high contrast marking and method thereof
View Patent ↗A power semiconductor device including a semiconductor die having electrically active first and second surfaces. A mark is located on the second surface configured to facilitate identification of the device and a metal layer is formed over the second surface of the semiconductor die and over the mark. The metal layer is configured to conduct a current of the device and to allow the mark to be visible for identification purposes.
1. A power semiconductor device, comprising:
a semiconductor die having a first surface and a second surface,
wherein the first and second surface are
electrically active;
a mark located on the second surface, the mark configured to facilitate the identification of the device;
a metal layer formed over the second surface of the semiconductor die and over the mark, the metal layer configured to conduct a current of the device and to allow the mark to be visible for identification purposes; and
a clip attached to the second surface of the semiconductor die for making an external electrical and mechanical connection.
2. The power semiconductor device of claim 1 , wherein a thickness of the semiconductor die is between about seventy-five and four-hundred micrometers.
3. The power semiconductor device of claim 1 , wherein the mark covers greater than about thirty-five percent of the second surface of the semiconductor die.
4. The power semiconductor device of claim 2 , wherein the metal layer is formed having a thickness greater than about fifteen thousand angstroms.
5. The power semiconductor device of claim 4 , wherein the metal layer is formed with a solderable back metal selected from the group consisting of nickel, silver, gold, nickel silicide, and nickel vanadium.
6. The power semiconductor device of claim 1 , wherein the current is greater than about 0.5 amperes.
7. The power semiconductor device of claim 1 , further comprising a conductive bump formed on the first surface of the semiconductor die for making an external electrical and mechanical connection.
8. The power semiconductor device of claim 1 , wherein the clip is formed of etched copper.
9. The power semiconductor device of claim 1 , further comprising a conductive bump formed on an external surface of the clip for making an external electrical and mechanical connection.
10. A semiconductor device, comprising;
a semiconductor substrate having a first surface,
wherein the first surface is electrically active to carry a current of the semiconductor device;
a mark located on the first surface, the mark configured to facilitate the identification of the device; and
a metal layer formed over the first surface of the semiconductor substrate and over the mark, the metal layer configured to conduct the current of the device and to allow the mark to be visible for identification purposes, wherein the metal layer is formed having a thickness greater than about fifteen thousand angstroms.
11. The semiconductor device of claim 10 , wherein a thickness of the semiconductor substrate is between about seventy-five and four-hundred micrometers.
12. The semiconductor device of claim 11 further comprising a clip for making an external electrical and mechanical connection attached to the metal layer.
13. The semiconductor device of claim 10 , wherein the metal layer is formed with a solderable back metal selected from the group consisting of nickel, silver, gold, nickel silicide, and nickel vanadium.
14. The semiconductor device of claim 10 , wherein the current is greater than about 0.5 amperes.
15. The semiconductor device of claim 10 , wherein the information includes an alphanumeric character having a height along the first surface less than about three hundred micrometers.
16. The semiconductor device of claim 10 , wherein the semiconductor substrate has a second surface opposite the first surface and formed having a conductive bump for making an external electrical and mechanical connection.
17. The semiconductor device of claim 12 , wherein the clip is formed of etched copper.
18. The semiconductor device of claim 17 , further comprising a conductive bump formed on an external surface of the clip for making the external electrical and mechanical connection.
19. A packaged semiconductor device, comprising;
a semiconductor chip having a first surface,
wherein the first surface is electrically active to carry a current of the semiconductor device;
a mark located on the first surface, the mark configured to facilitate the identification of the device; and
a solderable metal layer formed over the first surface of the semiconductor chip and over the mark, the solderable metal layer configured to conduct the current of the device and to allow the mark to be visible for identification purposes, wherein the solderable metal layer is formed having a thickness greater than about fifteen thousand angstroms, and wherein the solderable metal layer includes one of nickel, nickel vanadium, silver, or gold.
20. A method of making a semiconductor device, comprising the steps of:
providing a semiconductor substrate having a first electrically active surface for conducting a current of the semiconductor device;
removing substrate material to form a mark on the first electrically active surface, the mark configured to facilitate the identification of the device; and
forming a metal layer over the first electrically active surface of the semiconductor substrate and over the mark, the metal layer configured to conduct the current of the device and to allow the mark to be visible for identification purposes, wherein the metal layer has a thickness greater than about fifteen thousand angstroms.
21. The method of claim 20 , further comprising the step of attaching a conductive clip to the first electrically active surface for making an external electrical and mechanical connection.
22. The method of claim 20 , wherein the step of removing includes the step of forming an alphanumeric character with a font height along the first surface less than about three hundred micrometers in the substrate material.
23. The method of claim 20 , wherein the step of forming includes the step of forming a solderable metal layer comprising one of nickel, nickel vanadium, silver, or gold.