High-density three-dimensional memory
View Patent ↗An improved method for fabricating a three dimensional monolithic memory with increased density. The method includes forming conductors preferably comprising tungsten, then filling and planarizing; above the conductors forming semiconductor elements preferably comprising two diode portions and an antifuse, then filling and planarizing; and continuing to form conductors and semiconductor elements in multiple stories of memories. The arrangement of processing steps and the choice of materials decreases aspect ratio of each memory cell, improving the reliability of gap fill and preventing etch undercut.
1. A monolithic three-dimensional memory array comprising area density between 3.3×10 9 cells/mm 2 and 1.0×10 8 cells/mm 2 , wherein each cell comprises a semiconductor element sandwiched between a first conductor and a second conductor, wherein the semiconductor element is formed in a single patterning step, and wherein either of the conductors comprises tungsten.
2. The memory array of claim 1 , wherein the semiconductor element has a substantially cylindrical shape.
3. The memory array of claim 2 , wherein the semiconductor element comprises:
two portions of an incipient diode separated by an antifuse; or
a diode adjacent an antifuse.
4. The memory cell of claim 3 , wherein the semiconductor element comprises:
two portions of an incipient diode separated by an antifuse.
5. The memory cell of claim 3 , wherein the semiconductor element comprises:
a diode adjacent to an antifuse.
6. The memory cell of claim 5 , wherein the antifuse is above the diode.
7. The memory cell of claim 5 , wherein the antifuse is below the diode.
8. A monolithic three dimensional memory array comprising a cubic density greater than about 2.4×10 10 cells/mm 3 , wherein the memory array comprises memory cells, each memory cell comprising an antifuse and a diode.
9. The memory array of claim 8 wherein the cubic density is between 1.4×10 11 cells/mm 3 and 1.7×10 12 cells/mm 3 .
10. The memory array of claim 9 , comprising:
a plurality of substantially parallel first conductors; and
a plurality of first scmiconductor elements over the plurality of first conductors.