Digital potentiometer with resistor binary weighting decoding
View Patent ↗A digital potentiometer includes a string of impedance units in series. The string includes identical first and second sets of impedance units whose individual impedance values increment by a power of two. One of a plurality of switches is coupled in parallel with each respective impedance unit. The switches that are coupled to the first set of impedance units receive logical control signals complementary to logical control signals received by the respective switches coupled to the second set of impedance units, so that for every impedance unit of the first set that is bypassed (not bypassed), the identical impedance unit of the second set is not bypassed (bypassed). The string may include only the first and second sets of impedance units, or may include at least one third impedance unit in series with the first and second sets in a multi-stage design.
1. An integrated circuit, comprising:
a first set of at least two impedance units coupled in series between a first end and a second end thereof, wherein each of the impedance units has a different individual impedance value, and the individual impedance values increment across the set according to the formula I 0 *2 X , where I 0 is a selected base impedance value and X is a series of successive integers beginning with and including zero;
a second set of at least two impedance units coupled in series between a first end and a second end thereof, wherein the first and second sets of impedance units are in series and have a same number of impedance units and a same overall impedance, and each impedance unit of the second set has an individual impedance value equal to the individual impedance value of a corresponding one of the impedance units of the first set.
2. The integrated circuit of claim 1 , wherein the first and second sets of impedance units each extend in order of incrementing impedance from the first end of the respective set to the second end of the respective set.
3. The integrated circuit of claim 1 , wherein the first and second sets of impedance units are mirror images of each other.
4. The integrated circuit of claim 1 , wherein one of the first and second ends of the first set is coupled to one of the first and second ends of the second set at a central node.
5. The integrated circuit of claim 4 , wherein the first and second sets of impedance units are mirror images of each other with respect to the central node.
6. The integrated circuit of claim 1 , wherein the first set of impedance units extends in order of incrementing impedance from the first end of the first set to the second end of the first set, the second set of impedance units extends in order of incrementing impedance from the first end of the second set to the second end of the second set, and the second end of the first set is coupled to the second end of the second set.
7. The integrated circuit of claim 1 , further comprising:
a first set of switches, wherein each of the switches is coupled in parallel with a respective one of the impedance units of the first set of impedance units, with each switch being operable to bypass and not bypass the respective one of the impedance units with which the switch is coupled in parallel; and
a second set of switches, wherein each of the switches is coupled in parallel with a respective one of the impedance units of the second set of impedance units, with each switch being operable to bypass and not bypass the respective one of the impedance units with which the switch is coupled in parallel.
8. The integrated circuit of claim 7 , wherein one of the first and second ends of the first set is coupled to one of the first and second ends of the second set at a central node.
9. The integrated circuit of claim 8 , wherein the first and second sets of impedance units are mirror images of each other with respect to the central node.
10. The integrated circuit of claim 8 , wherein each of the switches of the first set of switches is coupled to receive a respective one of a first set of logical control signals, and each of the switches of the second set of switches is coupled to receive a respective one of a second set of logical control signals, the second set of logical control signals being complementary to the first set of logical control signals.
11. The integrated circuit of claim 8 , wherein the switches of the first and second sets that are coupled to the identical impedance value impedance units are coupled receive complementary logical control signals.
12. The integrated circuit of claim 7 , wherein each of the switches of the first set of switches is coupled to receive a respective one of a first set of logical control signals, and each of the switches of the second set of switches is coupled to receive a respective one of a second set of logical control signals, the second set of logical control signals being complementary to the first set of logical control signals.
13. The integrated circuit of claim 7 , wherein the switches of the first and second sets that are coupled to the identical impedance value impedance units are coupled receive complementary logical control signals.
14. The integrated circuit of claim 1 , further comprising at least one third impedance unit, wherein each said at least one third impedance unit is in series with the first and second sets of impedance units.
15. The integrated circuit of claim 14 , wherein the at least one third impedance unit has an impedance value equal to I 0 plus the combined impedance value of the first set of impedance units.
16. The integrated circuit of claim 15 , wherein the at least one third impedance unit is coupled between the first set of impedance units and the second set of impedance units, and the first and second sets of impedance units are mirror images of each other with respect to the at least one third impedance unit.
17. The integrated circuit of claim 14 , further comprising a plurality of third switches each having a first terminal and a second terminal,
wherein for each said at least one third impedance unit, the first terminal of a respective one of the third switches has its first terminal coupled to a first end of the third impedance unit, and another one of the third switches has its first terminal coupled to a second end of the third impedance unit, with each of the second terminals of the third switches being coupled to a common node.
18. The integrated circuit of claim 17 , wherein there are a plurality of the third impedance units coupled between the first and second sets of impedance units, and each of the third impedance units has an impedance value equal to I 0 plus the combined impedance value of the first set of impedance units.
19. The integrated circuit of claim 18 , wherein each of the third switches is coupled to receive a respective one of a third set of logical control signals from a decoder circuit.
20. The integrated circuit of claim 14 , wherein there are a plurality of pairs of the third impedance units, each having an identical impedance value, with one of the impedance units of each said pair is between the first set of at least two impedance units and a central node of a string including the first and second sets of at least two impedance units and the third impedance units, and the other impedance unit of the respective pair is between the central node and the second set of at least two impedance units.
21. The integrated circuit of claim 20 , further comprising a plurality of pairs of third switches, wherein each of the third switches has first and second terminals, with the first and second terminals each being coupled to an end of at least two of the third resistors.
22. An integrated circuit comprising:
a string of at least four impedance units coupled in series, wherein the at least four impedance units have different individual impedance values, the individual impedance values incrementing according to the formula I 0 *2 X , where I 0 is a selected base impedance value and X is a series of successive integers beginning with and including 0; and
a plurality of switches, wherein a respective one of the switches is coupled in parallel with each respective one of the impedance units.
23. The integrated circuit of claim 22 , wherein the string includes a plurality of pairs of the impedance units, wherein the two impedance units of each of the pairs have an identical individual impedance value, and the individual impedance values increment across all of the pairs according to the formula I 0 *2 X , where I 0 is a selected base impedance value and X is different one of a series of successive integers beginning with and including zero.
24. The integrated circuit of claim 23 , wherein the string includes a first set of the impedance units and a second set of the impedance units, wherein one of the impedance units of each of the pairs is in the first set, and the other impedance unit of each of the pairs is in the second set, the first and second sets being connected at a central node of the string.
25. The integrated circuit of claim 22 , wherein the string includes at least one third impedance unit having an impedance value different than the individual impedance value of any of the at least four impedance units.
26. The integrated circuit of claim 23 , wherein the string includes a first set of the impedance units and a second set of the impedance units, wherein one of the impedance units of each of the pairs is in the first set, and the other impedance unit of each of the pairs is in the second set, and
wherein the string further includes at least one third impedance unit, and each said at least one third impedance unit has an identical impedance value, the impedance value being selected from the group consisting of: (a) I 0 plus the combined impedance of the first set of impedance units; and (b) I 0 divided by 2 y −1, where y is the number of impedance units of the first set.
27. The integrated circuit of claim 26 , further comprising:
a plurality of third switches, wherein for each at least one third impedance unit, a first terminal of a respective one of the third switches is coupled to a first end of the respective third impedance unit, and a first terminal of another respective one of the third switches is coupled to a second end of the respective third impedance unit, and a second terminal of all of the third switches is coupled to a common node.
28. The integrated circuit of claim 22 , wherein the string includes a plurality of pairs of the impedance units, wherein the two impedance units of each of the pairs each have an identical individual impedance value, wherein the respective switches coupled to the respective impedance units of each said pair are coupled to receive complimentary logical control signals.
29. The integrated circuit of claim 28 , wherein the individual impedance values increment across all of the pairs according to the formula I 0 *2 X , where I 0 is a selected base impedance value and X is a different one of a series of successive integers beginning with and including zero.
30. The integrated circuit of claim 25 , wherein there are a plurality of pairs of the third impedance units in the string, each having an identical impedance value, and further comprising:
a plurality of pairs of second switches, wherein each of the third impedance units is bypassable by at least one of the second switches.
31. A method of operating a digital potentiometer, the method comprising:
providing an n-bit wiper address to a digital potentiometer comprising first and second sets of at least two switches each coupled to a string of at least four impedance units in series, wherein n is at least two and each said switch of the first set corresponds with one said switch of the second set;
using a first bit of the n-bit wiper address to control a first said switch of the first set, and a complement of the first bit to control the corresponding said switch of the second set; and
using a second bit of the n-bit wiper address to control a second said switch of the first set, and a complement of the second bit to control the corresponding said switch of the second set, the first and second bits being sequential in the n-bit wiper address.
32. The method of claim 31 , wherein each of the bits of the n-bit wiper address is used to control a respective one of the switches of the first set, and the complement of each of the bits of the n-bit wiper address is used to control the corresponding said switch of the second set.
33. The method of claim 31 , wherein n is at least three and the digital potentiometer includes a third set of at least two switches coupled to the string, and further comprising:
decoding at least a third bit of the n-bit wiper address to produce a plurality of decoded control signals; and
using each of the decoded control signals to control a respective one of the switches of the third set.
34. The method of claim 33 , wherein n is at least four, and the third bit and at least one other bit of the n-bit wiper address are decoded to produce the decoded control signals.
35. The method of claim 31 , wherein each said switch of the first and second sets of switches is coupled in parallel with a respective one of the impedance units, and is operable to bypass and not bypass the respective impedance unit.
36. The method of claim 35 , wherein the respective impedance units with which the respective switches of the first set are coupled in parallel have different individual impedance values, the individual impedance values incrementing according to the formula I 0 *2 X , where I 0 is a selected base impedance and X is a series of successive integers beginning with and including zero, and
wherein said each switch of the second set is coupled in parallel with a said impedance unit having an individual impedance value equal to the individual value of the impedance unit with which the corresponding switch of the first set is coupled in parallel.
37. A method of operating a digital potentiometer, the method comprising: providing an n-bit wiper address to a digital potentiometer comprising a string of in-series impedance units, the string including a plurality of pairs of the impedance units, the two impedance units of each pair having an identical individual impedance value, wherein n is at least two, and, wherein the individual impedance values increment across the pairs according to the formula I 0 *2 X , where I 0 is a selected base impedance value and X is different one of a series of successive integers beginning with and including zero; and, for each said pair of impedance units, in response to the n-bit wiper address, bypassing one impedance unit of the pair and not bypassing the other impedance unit of the pair.
38. The method of claim 37 , wherein whether one or the other of the two impedance units of each pair is bypassed depends on a state of a respective one of the bits of the n-bit wiper address.
39. A method of operating a digital potentiometer, the method comprising: providing an n-bit wiper address to a digital potentiometer comprising a string of in-series impedance units, the string including a plurality of pairs of the impedance units, the two impedance units of each pair having an identical individual impedance value, wherein n is at least two and, for each said pair of impedance units, in response to the n-bit wiper address, bypassing one impedance unit of the pair and not bypassing the other impedance unit of the pair, wherein whether one or the other of the two impedance units of each pair is bypassed depends on a state of a respective one of the bits of the n-bit wiper address.
40. The method of claim 39 , wherein there are n pairs of the impedance units.
41. A method of operating a digital potentiometer, the method comprising: providing an n-bit wiper address to a digital potentiometer comprising a string of in-series impedance units, the string including a plurality of pairs of the impedance units, wherein there are less than n pairs of the impedance units the two impedance units of each pair having an identical individual impedance value, wherein n is at least two and, for each said pair of impedance units, in response to the n-bit wiper address, bypassing one impedance unit of the pair and not bypassing the other impedance unit of the pair.
42. The method of claim 41 , wherein n is at least three, the string includes m pairs of the impedance units, m being at least two, and the string further comprises one or more third impedance units, the number of third impedance units being 2 (n−m) −1 and further comprising:
tapping the string at an end of at least one said third impedance unit in response to the n-bit wiper address.
43. The method of claim 41 , wherein n is at least three, the string includes m pairs of the impedance units, m being at least two, and the string further comprises a plurality of pairs of third impedance units, the number of third impedance units being 2*(2 (n−m) −1), and further comprising:
bypassing one of the third impedance units of each said pair of third impedance units, and not bypassing the other third impedance unit of the respective pair of third impedance units in response to the n-bit wiper address.