IP Library Granted Patent US 7,230,442
Granted Patent B2
US 7,230,442 · App. 10/860,594 · Granted Jun 12, 2007

Semi-conductor component testing process and system for testing semi-conductor components

Assignee: Infineon Technologies AG
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Quick Facts
Patent No.
US 7,230,442
App. No.
10/860,594
Granted
Jun 12, 2007
Kind
B2
Abstract

The invention involves a semi-conductor component testing process, and a system for testing semi-conductor components, in which a central computer device, in particular a central test apparatus is provided, with which test result data obtained from at least two separate tests is jointly evaluated, in particular by means of an appropriate pattern recognition process, which incorporates the test result data obtained from the separate tests into the analysis.

Claims (31)

1. A method for testing semiconductor components, comprising:

a training phase, comprising,

performing a first training test on a plurality of semiconductor devices to obtain first training test result data,

performing a second training test on the plurality of semiconductor devices to obtain second training test result data,

performing a third training test on the plurality of semiconductor devices to obtain third training test result data, and

analyzing the first training test result data, the second training test result data and the third training test result data to determine a pattern for semiconductor devices in which the first training test result data and the second training test result data indicate an acceptable semiconductor device and the third training result data indicates a failed semiconductor device, and

a testing phase, comprising,

performing a first test on a semiconductor device to obtain first test result data,

performing a second test on the semiconductor device to obtain second test result data, and

using a microprocessor based device to analyze the first test result data and the second test result data to predict if the semiconductor device would pass a third test based on the pattern determined in the training phase.

2. A system for testing semiconductor components, comprising:

a testing device,

to perform a first training test on a plurality of semiconductor devices to obtain first training test result data,

to perform a second training test on the plurality of semiconductor devices to obtain second training test result data,

to perform a third training test on the plurality of semiconductor devices to obtain third training test result data, and

to analyze the first training test result data, the second training test result data and the third training test result data to determine a pattern for semiconductor devices in which the first training test result data and the second training test result data indicate an acceptable semiconductor device and the third training result data indicates a failed semiconductor device,

to perform a first test on a semiconductor device, after the pattern is determined, to obtain first test result data, and

to perform a second test on the semiconductor device, after the pattern is determined, to obtain second test result data, and

a microprocessor based device to analyze the first test result data and the second test result data to predict if the semiconductor device would pass a third test based on the determined pattern.

3. A method for testing semiconductor components, comprising:

a training phase, comprising:

performing a first training test on a plurality of semiconductor components to obtain first training test result data;

performing a second training test on the plurality of semiconductor components to obtain second training test result data;

performing a third training test on the plurality of semiconductor components different from the first and second training test to obtain third training test result data; and

jointly analyzing the first training test result data, the second training test result data and the third training test result data to determine a pattern indicating an increased likelihood of a fault; and

a test phase, comprising:

performing a first test on a semiconductor component to obtain first test result data;

performing a second test on the semiconductor component to obtain second test result data; and

jointly analyzing the first and second test result data to predict whether the semiconductor component would pass a third test different from the first and second test based on the pattern determined in the training phase.

4. The method of claim 3 , wherein the step of jointly analyzing the first and second test result data comprises:

determining whether the first and second test result data are mutually correlated.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036873/0758 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023821/0535 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 1, 2007
From: MULLER, GEORG; KUND, MICHAEL
To: INFINEON TECHNOLOGIES AG
Reel/Frame 019231/0757 →
Priority Claims (1)
DE 103 26 338 · Jun 5, 2003 · national
Continuity (1)
Related Publication 20050017747A1 · Jan 27, 2005