MOS antifuse with low post-program resistance
View Patent ↗A semiconductor device having an increased intersection perimeter between edge regions of a first conductor and portions of a second conductor is disclosed. In one embodiment, the intersection perimeter is the region where the perimeter of a gate structure overlaps an active area. The intersection perimeter between the conductors directs the breakdown of the dielectric material, increasing the likelihood that the programming event will be successful. In at least one embodiment, the portion of a current path that travels through a highly doped area is increased while the portion that travels through a non-highly doped area is decreased. This decreases post-program resistance, leading to better response time for the device.
1. An antifuse on a chip comprising a dielectric material positioned between a conductor and an active area,
wherein the dielectric material having a first thickness,
wherein discrete portions of the dielectric material have a second thickness less than the first thickness where an edge portion of the conductor overlaps a first portion of a doped region of the active area,
wherein the first portion of the doped region is more highly doped directly beneath the edge portion of the conductor than is the first portion of the doped region elsewhere beneath the conductor,
wherein a short between the conductor and the active area passes through one or more of the discrete portions of the dielectric material programs the antifuse.
2. The anitfuse of claim 1 , wherein the dielectric material is in direct mechanical contact with both the conductor and the active area.
3. The anitfuse of claim 2 , wherein each discrete portion of the dielectric material where the second thickness is in direct mechanical contact with a trench of a plurality of isolation trenches disposed in the active area.
4. The anitfuse of claim 3 , wherein the first thickness of the dielectric material is oriented in a first direction, wherein the second thickness of the dielectric material is oriented in a second direction, and wherein the second direction is not parallel to the first direction.
5. The antifuse of claim 1 , wherein the first portion of the doped region is non-highly doped, wherein a second portion of the doped region that is not beneath the conductor is highly doped and is contiguous with the first portion of the doped region.
6. The antifuse claim 5 , wherein first and second portions of the doped region each comprise an N-type dopant.
7. The antifuse of claim 5 , wherein first and second portions of the doped region each comprise a P-type dopant.
8. An antifuse on a chip comprising a dielectric material positioned between a conductor and an active area,
wherein the dielectric material having a first thickness,
wherein discrete portions of the dielectric material have a second thickness less than the first thickness where an edge portion of one of the conductor and the active area overlaps the other of the conductor and the active area,
wherein a short between the conductor and the active area passes through one or more of the discrete portions of the dielectric material programs the antifuse,
wherein the short is induced by application of a voltage from an on-chip voltage source to one of the conductor and the active area.
9. The antifuse of claim 8 , wherein the voltage is not less than a programming voltage that causes the antifuse to become conductive, and wherein the programming voltage is substantially equal to a burn-in voltage at which the chip is tested for reliability.
10. An antifuse on a chip comprising a dielectric material positioned between a conductor and an active area,
wherein the dielectric material having a first thickness,
wherein discrete portions of the dielectric material have a second thickness less than the first thickness where an edge portion of one of the conductor and the active area overlaps the other of the conductor and the active area,
wherein a plurality or fingers are formed in the conductor,
wherein the fingers overlay a first portion of the active area,
wherein spaces between the plurality of fingers expose a second portion of the active area,
wherein the first portion of the active area comprises a non-highly doped region and the second portion of the active area comprises a highly-doped region, and
wherein the highly-doped region and the non-highly doped region comprise an N-type implant.
11. The anitfuse of claim 10 , wherein the edge portion of the conductor overlaps the active area.
12. The anitfuse of claim 10 , wherein the edge portion of the active area overlaps the conductor.
13. The anitfuse of claim 10 , wherein each discrete portion of the dielectric material where the second thickness is located is in direct mechanical contact with a trench of a plurality of isolation trenches disposed in the active area.
14. The anitfuse of claim 13 , wherein the first thickness of the dielectric material is oriented in a first direction, wherein the second thickness of the dielectric material is oriented in a second direction, and wherein the second direction is not parallel to the first direction.