IP Library Granted Patent US 7,202,106
Granted Patent B2
US 7,202,106 · App. 10/877,327 · Granted Apr 10, 2007

Multi-chip semiconductor connector and method

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Quick Facts
Patent No.
US 7,202,106
App. No.
10/877,327
Granted
Apr 10, 2007
Kind
B2
Abstract

In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is suitable for attaching to a first semiconductor die and a second conductive strip that is attached suitable for attaching to a second semiconductor die.

Claims (23)

1. A method of forming a multi-chip connector comprising:

forming a first semiconductor die attachment area on a first surface of a first conductive strip;

forming a second semiconductor die attachment area on a first surface of a second conductive strip; and

attaching a second surface of the first conductive strip to a second surface of the second conductive strip wherein the first semiconductor die attachment area on the first surface of the first conductive strip and the first semiconductor die attachment area on the first surface of the second conductive strip are each configured to provide both a mechanical attachment to a semiconductor die and a point for making an electrical connection to the semiconductor die.

2. The method of claim 1 wherein forming the first semiconductor die attachment area on the first conductive strip includes forming a raised semiconductor die attachment area.

3. The method of claim 1 wherein forming the second semiconductor die attachment area on the first surface of the second conductive strip includes forming a raised semiconductor die attachment area.

4. The method of claim 1 wherein attaching the second surface of the first conductive strip to the second surface of the second conductive strip includes attaching the second surface of the first conductive strip to a first surface of an insulator and attaching the second surface of the second conductive strip to a second surface of the insulator.

5. The method of claim 1 wherein attaching the second surface of the first conductive strip to the second surface of the second conductive strip includes attaching the second surface of the first conductive strip to a first surface of a semiconductor die and attaching the second surface of the second conductive strip to a second surface of the semiconductor die.

6. The method of claim 1 further including forming the first conductive strip as a portion of a first leadframe strip of a first leadframe panel and forming the second conductive strip as a portion of a first leadframe strip of a second leadframe panel.

7. A method of forming a multi-chip connector comprising:

forming a first semiconductor die attachment area on a first surface of a first conductive strip as one of a ball-bond semiconductor die attachment area or a solder semiconductor die attachment or a portion of a material used to form the first conductive strip;

forming a second semiconductor die attachment area on a first surface of a second conductive strip as one of a ball-bond semiconductor die attachment area or a solder semiconductor die attachment or a portion of a material used to form the second conductive strip; and

attaching a second surface of the first conductive strip to a second surface of the second conductive strip.

8. A method of forming a multi-chip connector comprising:

forming a first semiconductor die attachment area on a first surface of a first conductive strip;

forming a second semiconductor die attachment area on a first surface of a second conductive strip; and

attaching a second surface of the first conductive strip to a second surface of the second conductive strip wherein the first semiconductor die attachment area on the first surface of the first conductive strip and the first semiconductor die attachment area on the first surface of the second conductive strip are configured to provide a direct electrical connection to a semiconductor die without the use of bonding wires.

9. The method of claim 8 wherein forming the first semiconductor die attachment area on the first conductive strip includes forming a raised semiconductor die attachment area.

10. The method of claim 8 wherein forming the second semiconductor die attachment area on the first surface of the second conductive strip includes forming a raised semiconductor die attachment area.

11. The method of claim 8 wherein forming the first semiconductor die attachment area and forming the second semiconductor die attachment area includes forming one of a ball-bond semiconductor die attachment area or a solder semiconductor die attachment or a portion of a material used to form which the first conductive strip.

12. The method of claim 8 wherein attaching the second surface of the first conductive strip to the second surface of the second conductive strip includes attaching the second surface of the first conductive strip to a first surface of an insulator and attaching the second surface of the second conductive strip to a second surface of the insulator.

13. The method of claim 8 wherein attaching the second surface of the first conductive strip to the second surface of the second conductive strip includes attaching the second surface of the first conductive strip to a first surface of a semiconductor die and attaching the second surface of the second conductive strip to a second surface of the semiconductor die.

14. The method of claim 8 further including forming the first conductive strip as a portion of a first leadframe strip of a first leadframe panel and forming the second conductive strip as a portion of a first leadframe strip of a second leadframe panel.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT AND COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038631/0345 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: JPMORGAN CHASE BANK, N.A. (ON ITS BEHALF AND ON BEHALF OF ITS PREDECESSOR IN INTEREST, CHASE MANHATTAN BANK)
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038632/0074 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2005
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 016183/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 28, 2004
From: CARNEY, FRANCIS J.; CELAYA, PHILLIP; FAUTY, JOSEPH A.; LETTERMAN, JAMES P.; ST. GERMAIN, STEPHEN; YODER, JAY A.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, L.L.C.
Reel/Frame 015526/0121 →