IP Library Granted Patent US 7,041,582
Granted Patent B2
US 7,041,582 · App. 10/878,478 · Granted May 9, 2006

Method of manufacturing semiconductor device

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Quick Facts
Patent No.
US 7,041,582
App. No.
10/878,478
Granted
May 9, 2006
Kind
B2
Abstract

The present invention relates to a method of manufacturing a semiconductor device. A barrier metal layer for blocking a metal material from being diffused into an insulating film is formed by means of an ALD method. At this time, the barrier metal layer is formed to have an amorphous structure and the barrier metal layer at the bottom of a contact hole or a via hole is selectively removed so that the barrier metal layer having good anti-diffusion properties even in a thin thickness is obtained. Therefore, it is possible to prevent resistance from increasing due to the barrier metal layer.

Claims (26)

1. A method of manufacturing a semiconductor device, comprising:

a) providing a semiconductor substrate on which various components for forming a semiconductor device are formed;

b) supplying a precursor containing a source into a deposition chamber to adsorb the source on the semiconductor substrate;

c) removing the precursor which is not absorbed on the semiconductor substrate and remains in the deposition chamber to purify the interior of the deposition chamber, wherein other impurities are removed with the precursor;

d) supplying a reaction gas into the deposition chamber to form an atomic layer through reaction with the source adsorbed on the semiconductor substrate;

e) removing the reaction gas which is not reacted with the source to purify the interior of the deposition chamber, wherein reaction byproducts are removed with the reaction gas;

f) supplying an additive gas into the deposition chamber in order to make the atomic layer an amorphous state; and

g) removing the additive gas to purify the interior of the deposition chamber.

2. The method as claimed in claim 1 , wherein one cycle consisting of the step a) through step e) is repeated at least one time.

3. The method as claimed in claim 1 , the step a) including: forming an interlayer insulating film on a semiconductor substrate; and forming a via hole or a trench in the interlayer insulating film.

4. The method as claimed in claim 3 , wherein a barrier metal layer of an amorphous state is formed on an entire surface of the interlayer insulating film by repeating one cycle consisting of the step a) through step e) at least one time.

5. The method as claimed in claim 4 , wherein the precursor containing the source is a material of a metal organic source or a halide compound.

6. The method as claimed in claim 5 , wherein the precursor containing the source is a metal organic source such as PDMAT or TBTDET.

7. The method as claimed in claim 5 , wherein the precursor containing the source is a halide compound such as TaCl 5 , TaBr 5 or Tal 5 .

8. The method as claimed in claim 4 , wherein the additive gas is removed with Ar, N 2 or He gas.

9. The method as claimed in claim 4 , wherein the reaction gas includes a nitrogen mixed gas.

10. The method as claimed in claim 9 , wherein the nitrogen mixed gas includes an N 2 or NH 3 gas.

11. The method as claimed in claim 4 , wherein the reaction gas and the source are reacted by means of a heating method or a method for generating plasma within a chamber to introduce reaction.

12. The method as claimed in claim 4 , wherein the reaction gas and the source are reacted at a temperature of 100° C. to 400° C.

13. The method as claimed in claim 4 , wherein the second to seventh steps are each performed for 0.1 to 5 seconds.

14. The method as claimed in claim 4 , wherein the barrier metal layer of the atomic layer is formed using Ta, TaN, TaC, WN, TiN, TiW, TiSiN, WBN or WC.

15. The method as claimed in claim 4 , wherein the sixth and seventh step are further performed whenever the 1 cycle is performed, or performed whenever the 1 cycle is performed several to several tens of times.

16. The method as claimed in claim 4 , wherein the additive gas includes a gas containing O, C or H components, or a mixed gas thereof.

17. The method as claimed in claim 4 , wherein the additive gas includes an O 2 , CO, CO 2 , H 2 or NH 3 gas.

18. The method as claimed in claim 4 , wherein the partial pressure within a chamber of the additive gas is set to 10 −3 torr to 10 torr.

19. The method as claimed in claim 4 , wherein the precursor including the source, the reaction gas, the additive gas and the purification gas are supplied into the deposition chamber through different supply lines.

Assignments (4)
CHANGE OF NAME Recorded Mar 12, 2024
From: KEY FOUNDRY CO., LTD.
To: SK KEYFOUNDRY INC.
Reel/Frame 066794/0290 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2020
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: KEY FOUNDRY CO., LTD.
Reel/Frame 053703/0227 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 5, 2009
From: HYNIX SEMICONDUCTOR INC.
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 023056/0279 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 25, 2004
From: MIN, WOO SIG
To: HYNIX SEMICONDUCTOR INC.
Reel/Frame 015730/0291 →