Semiconductor device having pad structure for preventing and buffering stress of silicon nitride film
View Patent ↗The present invention discloses a semiconductor device having a pad structure for preventing a stress of a silicon nitride film. The semiconductor device includes a semiconductor substrate, a lower structure formed on the semiconductor substrate, a first insulation film formed on the lower structure, a first metal layer coupled to the lower structure through a first metal contact in the first insulation film, a second metal layer formed on the first metal layer, and a plurality of dummy gates having a concentric square structure formed at the lower portion of the pad region on the second metal layer.
1. A semiconductor device, comprising:
a semiconductor substrate;
a field oxide film on the semiconductor substrate;
a plurality of inside dummy gates formed on the field oxide film under a pad region;
an outside dummy gate for surrounding the pad region at a predetermined interval from the pad region outside the pad region;
a silicon nitride film formed on an entire structure including the plurality of inside dummy gates;
an insulation film formed over an entire structure including the silicon nitride film;
a metal layer formed over the insulating film for forming a pad at the pad region; and
a protection layer formed on a portion of the metal layer,
wherein the pad region of the metal layer is exposed, and the exposed metal layer is used as the pad to supply a voltage from outside of the semiconductor device to inside of the semiconductor device, according to a wire bonding process.
2. The semiconductor device of claim 1 , wherein the inside dummy gates are formed in the shape of a plurality of concentric squares or a plurality of islands.
3. The semiconductor device of claim 1 , wherein a horizontal interval between the inside dummy gates and the edges of the pad region ranges from 0.3 to 3.0 μm.
4. The semiconductor device of claim 1 , wherein a width of the inside dummy gates ranges from 0.3 to 3.0 μm.
5. The semiconductor device of claim 1 , wherein an interval between the inside dummy gates ranges from 0.3 to 3.0 μm.
6. A semiconductor device, comprising:
a semiconductor substrate;
a lower structure formed on the semiconductor substrate;
an insulation film formed over an entire structure including the lower structure;
a metal layer formed over the insulating film for forming a pad at a pad region;
a plurality of inside dummy gates formed under the pad region;
an outside dummy gate for surrounding the pad region at a predetermined interval from the pad region outside the pad region; and,
a silicon nitride film formed on an entire structure including the plurality of inside dummy gates.
7. The semiconductor device of claim 6 , wherein a width of the outside dummy gate ranges from 0.3 to 1.0 μm.
8. The semiconductor device of claim 6 , wherein a horizontal interval between the outside dummy gate and the pad region ranges from 2.0 to 5.0 μm.
9. The semiconductor device of claim 6 , further comprising a first dummy metal contact etched in a line shape on the outside dummy gate outside the pad region.
10. The semiconductor device of claim 9 , wherein a width of the first dummy metal contact ranges from 0.2 to 0.4 μm.
11. The semiconductor device of claim 9 , wherein the first dummy metal contact is formed on the outside dummy gate.
12. The semiconductor device of claim 1 , wherein a width of the outside dummy gate ranges from 0.3 to 1.0 μm.
13. The semiconductor device of claim 1 , wherein a horizontal interval between the outside dummy gate and the pad region ranges from 2.0 to 5.0 μm.
14. The semiconductor device of claim 1 , further comprising a first dummy metal contact etched in a line shape on the outside dummy gate outside the pad region.
15. The semiconductor device of claim 14 , wherein a width of the first dummy metal contact ranges from 0.2 to 0.4 μm.
16. The semiconductor device of claim 14 , wherein the first dummy metal contact is formed on the outside dummy gate.