Control of memory arrays utilizing zener diode-like devices
View Patent ↗The present invention facilitates semiconductor devices by aiding the efficiency in the way individual devices change states in a semiconductor array. State change voltages can be applied to a single device in the array of semiconductor devices without the need for transistor-type voltage controls. The diodic effect of the present invention facilitates this activity by allowing specific voltage levels necessary for state changes to only occur at the desired device. In this manner, an array of devices can be programmed with varying data or states without utilizing transistor technology. The present invention also allows for an extremely efficient method of producing these types of devices, eliminating the need to manufacture costly external voltage controlling semiconductor devices.
1. A semiconductor device comprising:
at least one organic memory cell that has a selectively conductive organic layer coupled to a first electrode, the selectively conductive organic layer comprises a passive layer and an organic conductor layer; and
a diodic layer formed on the selectively conductive organic layer.
2. The device of claim 1 , the diodic layer has reverse-zener-type characteristics.
3. The device of claim 2 , the diodic layer has electrical characteristics approximately defined by:
| V PROG |>|V ERASE |>|V READ | (C).
4. The device of claim 3 , the electrical characteristics further approximately defined by:
| V REVERSE BREAKDOWN |>|V FORWARD TURN ON | (B).
5. The device of claim 3 , the diodic layer provides a resistive loading element for programming of the memory cell.
6. The device of claim 1 , the organic memory cell comprising a second electrode, the selectively conductive organic layer interposed between the first and second electrodes.
7. The device of claim 6 , the first electrode comprising a material composed of at least one of copper and aluminum.
8. The device of claim 6 , the second electrode comprising a material composed of at least one of copper and aluminum.
9. The device of claim 6 , the diodic layer comprising a third electrode and a thin film layer interposed between the second electrode and the third electrode.
10. The device of claim 6 , the diodic layer comprises the second electrode and a thin film layer interposed between the selectively conductive organic layer and the second electrode.
11. The device of claim 1 , the organic memory cell comprises an organic light emitting diode (OLED).
12. The device of claim 1 , the organic memory cell comprising an EEPROM cell.
13. A memory array comprising a plurality of the semiconductor devices of claim 1 .
14. A semiconductor device comprising:
at least one organic memory cell; and
a diodic layer coupled to the at least one organic memory cell, the diodic layer has reverse zener-type diodic properties with a forward voltage level sufficient to cause the memory cell to operate and a breakdown voltage level that causes the memory cell to be programmed.
15. The device of claim 14 , the diodic layer comprising a first layer coupled to the organic memory cell and a second layer coupled to the first layer.
16. The device of claim 15 , the first and second layers forming at least one of a silicon based p-n junction, an organic-organic semiconductor junction, an organic semiconductor-metal junction, an organic semiconductor-silicon based p-type material junction, and an organic semiconductor-silicon based n-type material junction.
17. The device of claim 15 , the first layer comprising a polysilicon material.
18. The device of claim 15 , the first layer comprising a material composed of organic and inorganic conducting material.
19. The device of claim 15 , the first layer comprising a semiconductor material in an amorphous state.
20. The device of claim 15 , the first layer comprising a semiconductor material in a crystal state.
21. The device of claim 15 , the first layer comprising a thin film layer.
22. The device of claim 15 , the first layer comprising a multi-thin film layer.
23. The device of claim 15 , the second layer comprising a material composed of at least one of copper and aluminum.
24. A method of fabricating a semiconductor device comprising:
forming a first layer on a memory cell; and
forming a second layer on the first layer to create a diodic junction with the first layer, the diodic junction has reverse zener-type properties with a forward voltage level sufficient to cause the memory cell to operate and a selectable breakdown voltage level sufficient to cause the memory cell to be programmed.
25. The method of claim 24 , wherein forming the first layer comprises a thin film formation process.
26. The method of claim 24 , wherein forming the first layer comprises a multi-thin film formation process.
27. The method of claim 24 , wherein the second layer forms the top electrode of the semiconductor device.
28. The method of claim 24 , further comprising:
forming a first electrode;
forming a selectively conductive organic layer on the first electrode; and
forming a second electrode on the selectively conductive organic layer, providing an electrode for the semiconductor cell.
29. A memory cell array comprising a plurality of addressable memory cell devices that have diodic characteristics which enable self-regulation of internal current flow for programming, erasing and reading purposes, wherein a diodic layer is coupled to at least one memory cell that has a selectively conductive organic layer comprising a passive layer and an organic conductor layer.
30. The memory cell array of claim 29 , the diodic characteristics comprise a resistive loading element that is employed to program an addressable memory cell device.
31. The memory cell array of claim 29 , the diodic layer exhibits reverse-zener-type diodic properties.
32. The memory cell array of claim 31 , the diodic layer has a forward voltage level sufficient to cause the memory cell to operate.
33. The memory cell array of claim 31 , the diodic layer has a breakdown voltage level sufficient to cause the memory cell to be programmed.