Method of reference cell design for optimized memory circuit yield
View Patent ↗A method for standard reference cell design is herein disclosed. The method includes determining a first number of individual bits to be employed in a standard reference cell design based on the number of individual bits that are included in core memory cells that are to be measured using the standard reference cell. The method further includes determining a range of variation in the core memory cells to be measured that is due to process variation in the generation of the core memory cells. In addition, the method includes determining an additional number of individual bits to be included in the standard reference cell design based on the determined range of variation. A standard reference cell that includes a number of individual bits equal to the sum of both the first and the additional number of individual bits is generated.
1. A method for standard reference cell generation comprising:
determining a first number of individual reference cells to be employed in a standard reference cell design based on memory cells to be measured;
determining a range of variation due to process variation in the generation of said memory cells to be measured;
determining an additional number of individual reference cells to be included in said standard reference cell design based on said range of variation; and
generating a standard reference cell that includes a number of individual reference cells equal to the sum of said first and said additional number of individual reference cells.
2. The method of claim 1 , wherein said variation is caused by differences in implantation process.
3. The method of claim 2 , wherein said variation is caused by a difference in source resistance shown by said memory cells.
4. The method of claim 3 , wherein said source resistance varies by as much as 10 percent.
5. The method of claim 3 , wherein the current capacity of said memory cells vary with said source resistance.
6. The method of claim 5 , wherein a memory cell comprises a transistor.
7. The method of claim 1 , wherein said memory cells are flash memory cells.
8. A method for standard reference cell design:
determining a first number of individual bits to be employed in a standard reference cell design based on the number of individual cells that are contained in core memory cells to be measured;
determining a worst case variation due to process variation in the generation of said core memory cells to be measured;
determining an additional number of individual bits to be included with said first number of individual bits in said standard reference cell design based on said worst case variation; and
generating a standard reference cell that includes a number of individual bits equal to the sum of said first number of individual bits and said additional number of individual bits.
9. The method of claim 8 , wherein said variation is caused by differences in an implantation process that is employed in the manufacture of said core memory cells.
10. The method of claim 9 , wherein said variation is caused by a difference in the source resistances shown by said core memory cells.
11. The method of claim 10 , wherein said source resistances vary by as much as 10 percent.
12. The method of claim 11 , wherein the current capacity of said core memory cells vary with said source resistances.
13. The method of claim 12 , wherein a memory cell comprises a transistor.
14. The method of claim 8 , wherein said core memory cells are flash memory cells.
15. A method for standard reference cell design:
determining a first amount of source resistance to be employed in a standard reference cell design based on core memory cells to be measured;
determining a range of variation due to process variation in the generation of said core memory cells to be measured;
determining an additional amount of source resistance to be included in said standard reference cell design based on said range of variation; and
generating a standard reference cell that includes a source resistance equal to the sum of said first and said additional amount of source resistance.
16. The method of claim 15 , wherein said variation is caused by differences in an implantation process employed in the manufacture of said core memory cells.
17. The method of claim 16 , wherein said variation is caused by a difference in source resistance shown by said core memory cells.
18. The method of claim 17 , wherein said source resistance varies by as much as 10 percent.
19. The method of claim 18 , wherein the current capacity of said core memory cells varies with said source resistance.
20. The method of claim 19 , wherein a memory cell comprises a transistor.
21. The method of claim 15 , wherein said memory cells are flash memory cells.
22. A standard reference cell comprising:
a first number of individual reference cells; and
an additional number of individual reference cells;
wherein said first number of individual reference cells correspond to the number of individual memory cells contained in core memory cells to be measured and wherein further said additional number of individual reference cells correspond to a determined range of variation of the source resistances of the core memory cells.
23. The method of claim 22 , wherein said variation is caused by differences in an implantation process employed in the manufacture of said core memory cells.
24. The method of claim 23 , wherein said source resistances vary by as much as 10 percent.
25. The method of claim 22 , wherein said core memory cells are flash memory cells.
26. The method of claim 25 , wherein the current capacity of said core memory cells vary with said source resistances.
27. The method of claim 26 , wherein an individual reference cell comprises a transistor.