Semiconductor device employing SOI substrate and method of manufacturing the same
View Patent ↗A semiconductor device employing a PD-SOI substrate and a method of manufacturing the same are capable of minimizing a floating body effect. The semiconductor device employs a silicon layer over a buried insulating layer on a silicon wafer, isolating layers in the silicon layer in contact with the buried insulating layer, a body layer of a first conductivity type in the silicon layer between the isolating layers and having a trench, a gate insulating layer and a gate electrode in the trench of the body layer, a spacer on the sidewall of the gate electrode, LDD regions of a second conductivity type in the body layer on both sides of the gate electrode in contact with the buried insulating layer under the trench, and source and drain regions of the second conductivity type the body layer on both sides of the spacer in contact with the buried insulating layer.
1. method of manufacturing a semiconductor device comprising:
in a SOI substrate having a silicon layer over a buried insulating layer on a silicon wafer, forming isolating layers adjacent to the silicon layer in contact with the buried insulating layer;
forming a body layer having a first conductivity type in the silicon layer between the isolating layers;
forming a hard mask exposing a portion of the body layer, etching the exposed portion of the body layer, and removing the hard mask to form a trench in the body layer;
forming a gate insulating layer on the entire surface of the trench;
forming a gate electrode on the gate insulating layer, the gate electrode being narrower than the trench;
forming LDD regions having a second conductivity type in the body layer of both sides of the gate electrode, in contact with the buried insulating layer under the trench, and aligned to sidewalls of the gate electrode;
forming a spacer on the sidewalls of the gate electrode;
forming source and drain regions having the second conductivity type in the body layer of both sides of the spacer, in contact with the buried insulating layer; and
after forming the source and drain regions, forming silicide layers on the surfaces of the gate electrode and the LDD regions.
2. The method of claim 1 , wherein the trench is separated from the buried insulating layer by a predetermined space.
3. The method of claim 2 , wherein the space between the trench and the buried insulating layer is 100 Å to 500 Å.
4. The method of claim 1 , wherein the hard mask compries a nitride layer.
5. The method of claim 1 , wherein the spacer is formed in contact with the gate insulting layer on the side portion of the trench.
6. The method of claim 1 , further comprising forming a buffer insulating layer between the steps of forming the LDD regions and forming the spacer.
7. The method of claim 1 , wherein the first conductive type comprises a P type and the second conductive type comprises an N type.
8. The method of claim 1 , wherein the SOI substrate comprises a partially depleted type SOI substrate.
9. The method of claim 1 , comprising forming the LDD regions before forming the spacer.