Apparatus and method for a memory array with shallow trench isolation regions between bit lines for increased process margins
View Patent ↗The present invention provides an apparatus and method for a non-volatile memory comprising at least one array of memory cells with shallow trench isolation (STI) regions between bit lines for increased process margins. Specifically, in one embodiment, each of the memory cells in the array of memory cells includes a source, a control gate, and a drain, and is capable of storing at least one bit. The array of memory cells further includes word lines that are coupled to control gates of memory cells. The word lines are arranged in rows in the array. In addition, the array comprises bit lines coupled to source and drains of memory cells. The bit lines are arranged in columns in the array. Also, the array comprises at least one row of bit line contacts for providing electrical conductivity to the bit lines. Further, the array comprises shallow trench isolation (STI) regions separating each of the bit lines along the row of bit line contacts.
1. A non-volatile memory comprising at least one array of memory cells, wherein each of the memory cells comprising a source, a control gate, and a drain, and capable of storing at least one bit, said array of memory cells further comprising:
a plurality of word lines coupled to control gates of said memory cells, said plurality of word lines arranged in rows in said array;
a plurality of bit lines individually coupled to both said source and said drain of each of said memory cells, wherein said source and said drain are separated by a channel region and wherein said plurality of bit lines are arranged in columns in said array;
at least one row of bit line contacts for providing electrical conductivity to said plurality of bit lines;
a plurality of shallow trench isolation (STI) regions separating each of said plurality of bit lines along said at least one row of bit line contacts;
a plurality of side-wall spacers separating neighboring word lines from said plurality of STI regions and
a cobalt silicide (COSI) layer formed between bit line contacts in said at least one row of contacts and said plurality of bit lines.
2. The non-volatile memory of claim 1 , wherein said side-wall spacers are composed of silicon nitride (SiN).
3. The non-volatile memory of claim 1 , further comprising:
an oxide-nitride-oxide (ONO) layer under said plurality of word lines, wherein said ONO layer is removed between said plurality of word lines, and over said plurality of STI regions.
4. The non-volatile memory of claim 1 , further comprising:
a plurality of N+ regions defining a contact region for forming said contacts in said at least one row of contacts.
5. The non-volatile memory of claim 1 , further comprising:
wherein said memory cells comprise dual bit flash memory cells.
6. A non-volatile memory comprising at least one array of memory cells, wherein each of the memory cells comprises a source, a control gate, and a drain, and is capable of storing at least one bit, said array of memory cells further comprising:
a plurality of shallow trench isolation (STI) regions separating each of a plurality of bit lines for promoting a wider process margin when aligning contacts in at least one row of bit line contacts to said plurality of bit lines, wherein said plurality of STI regions is arranged in a row corresponding to said at least one row of bit line contacts, and wherein said plurality of bit lines are respectively coupled to a source and a drain of a memory cell and are arranged in columns in said array; and
a plurality of cobalt silicide (COSI) layers formed between bit line contacts in said at least one row of contacts and said plurality of bit lines, wherein said plurality of STI regions prevent the formation of bit line to bit line shorts wherein STI is used as an alignment mark for the formation of said plurality of bit lines, said plurality of word lines, and a plurality of contacts that are electrically coupled to said plurality of bit lines.
7. The non-volatile memory of claim 6 , further comprising:
wherein said memory cells comprise dual bit flash memory cells.