Method and apparatus for minimizing threshold variation from body charge in silicon-on-insulator circuitry
View Patent ↗Circuitry used to de-skew data channels coupling parallel data signals over a communication link employs SOI circuitry that is subject to generating pulse distortion due to the history effect modifying threshold voltages. To substantially eliminate the pulse distortion, data signals are XOR with a repeating scramble data pattern that generates scrambled data with a minimum average ratio of logic ones to logic zeros logic zeros to logic ones. The scrambled data is sent over the communication link and de-skewed in the SOI circuitry with little or no pulse distortion. The scramble data pattern is again generated at the receiver side of the communication link after a delay time to synchronize the logic states of the scramble data pattern that generated the scrambled data with the scrambled data at the receiver side. The delayed scrambled data pattern is again XOR'ed with the scrambled data to recover the data signal.
1. A method of minimizing pulse distortion in a silicon-on-insulator (SOI) first circuit receiving data over a data channel from a second circuit separated from the first circuit comprising the steps of:
generating an N bit scramble bit pattern at the second circuit having a predetermined ratio of logic one states to logic zero states;
generating a scrambled data pattern as a first logic exclusive OR (XOR) combination of first data from the second circuit and the N bit scramble bit pattern synchronized as a synchronized N bit scramble bit pattern;
transmitting the scrambled data pattern over the data channel through the first circuit to an output of the first circuit;
generating the synchronized N bit scramble bit pattern at the first circuit with a propagation delay time; and
recovering the first data from the transmitted scrambled data pattern as detected first data by a second logic XOR combination of the scrambled data pattern coupled from the output of the first circuit and the synchronized N bit scramble bit pattern generated at the first circuit.
2. The method of claim 1 , wherein the N is equal to 64.
3. The method of claim 1 , wherein the synchronized N bit scramble bit pattern is generated by starting the N bit scramble bit pattern using a 4 bit sync bit pattern within the N bit scramble bit pattern.
4. The method of claim 3 , wherein the propagation delay time is the time for a sync bit in the sync bit pattern to propagate from the second circuit to the output of the first circuit.
5. The method of claim 4 , wherein the N bit scramble bit pattern assures that the scramble data pattern has an average ratio of logic one states to logic zero states greater than or equal to 25 percent.
6. The method of claim 3 , wherein the N bit scramble bit pattern is consecutive bits 0 through 63 defined as sixteen 4 bit hex bytes [926F4A736F4A5328], the first byte starting at bit 0 , the sixteenth hex byte starting at bit 60 .
7. The method of claim 6 , wherein bits 61 , 62 , 63 and 0 of the N bit scramble bit pattern define the 4 bit sync bit pattern and the first and second XOR combinations of the first data with the N bit scramble bit pattern commence at bit 0 .
8. The method of claim 1 , wherein the first circuit is a programmable delay circuit for phase aligning the data channel with a plurality of like data channels, wherein the data channel and the plurality of like data channel communicate parallel bits of data signal.
9. The method of claim 1 , wherein the second circuit is a latch holding circuit that outputs the first data in response to a first transition of a first clock signal.
10. The method of claim 9 , wherein the detected first data is clocked into a latch holding circuit in response to the first transition of a second clock signal of the same frequency and synchronous with the first clock signal.
11. A data processing system comprising:
a central processing system (CPU);
a random access memory (RAM); and
a bus coupling the CPU and the RAM, wherein the CPU has a first and a second integrated circuit (IC) communicating parallel data bits over a data channel, the first IC having a silicon-on-insulator (SOI) first circuit receiving data over the data channel from a second circuit in the second IC, wherein the second IC has circuitry for generating an N bit scramble bit pattern at the second circuit having a predetermined ratio of logic one states to logic zero states, circuitry for generating a scrambled data pattern as a first logic exclusive OR (XOR) combination of first data from the second circuit and the N bit scramble bit pattern synchronized as a synchronized N bit scramble bit pattern, circuitry for transmitting the scrambled data pattern over the data channel through the first circuit to an output of the first circuit, circuitry for generating the synchronized N bit scramble bit pattern at the first circuit with a propagation delay time, and circuitry for recovering the first data from the transmitted scrambled data pattern as detected first data by a second logic XOR combination of the scrambled data pattern coupled from the output of the first circuit and synchronized N bit scramble bit pattern generated at the first circuit.
12. The data processing system of claim 11 , wherein the number N is equal to 64.
13. The data processing system of claim 11 , wherein the synchronized N bit scramble bit pattern is generated by starting the N bit scramble bit pattern using a 4 bit sync bit pattern within the N bit scramble bit pattern.
14. The data processing system of claim 13 wherein the propagation delay time is the time for a sync bit in the sync bit pattern to propagate from the second circuit to the output of the first circuit.
15. The data processing system of claim 13 , wherein the N bit scramble bit pattern is consecutive bits 0 through 63 defined as sixteen 4 bit hex bytes [926F4A736F4A5328], the first byte starting at bit 0 , the sixteenth hex byte starting at bit 60 .
16. The data processing system of claim 15 , wherein bits 61 , 62 , 63 and 0 of the N bit scramble bit pattern define the 4 bit sync bit pattern and the first and second XOR combinations of the first data with the N bit scramble bit pattern commence at bit 0 .
17. The data processing system of claim 11 , wherein the first circuit is a programmable delay circuit for phase aligning the data channel with a plurality of like data channels, wherein the data channel and the plurality of like data channel communicate parallel bits of data signal.
18. The data processing system of claim 11 , wherein the N bit scramble bit pattern assures that the scramble data pattern has an average ratio of logic one states to logic zero states greater than or equal to 25 percent.
19. The data processing system of claim 11 , wherein the second circuit is a latch holding circuit that outputs the first data in response to a first transition of a first clock signal.
20. The data processing system of claim 19 , wherein the detected first data is clocked into a latch holding circuit in response to the first transition of a second clock signal of the same frequency and synchronous with the first clock signal.