Gate conductor isolation and method for manufacturing same

1. A method for processing a semiconductor device comprises:

providing the semiconductor device including a deep trench transistor in an array area and a shallow trench isolation oxide in a support area, wherein a pad oxide and pad nitride are sequentially formed on a semiconductor substrate;

stripping the pad nitride;

depositing an array top oxide layer over the semiconductor device;

planarizing the array top oxide to a top of the shallow trench isolation oxide in the support area and to a deep trench poly stud of the deep trench transistor in the array area;

forming a wordline stack comprising a polysilicon-layer, a gate conductor and an insulator-formed sequentially on the array top oxide; and

etching the array top oxide, forming a passing wordline bridge through the array area supported on the shallow trench isolation oxide.

2. The method of claim 1 , wherein the pad nitride is stripped from the array area, wherein the pad nitride remains in the support area.

3. The method of claim 1 , wherein the pad nitride is stripped from the array area and the support area.

4. The method of claim 1 , further comprising depositing a support area polysilicon.

5. The method of claim 1 , wherein forming the wordline stack comprises:

depositing a photoresist;

patterning the photoresist to expose portions of the insulator; and

etching the exposed portions of the insulator and the underlying gate conductor, polysilicon and array top oxide.

6. The method of claim 1 , wherein the etching removes portions of a support area polysilicon.