Low-voltage differential signal (LVDS) transmitter with high signal integrity
View Patent ↗A differential signal output driver circuit having four switching transistors and having a bias transistor that shields each of the switching transistors from the corresponding output terminal thereby blocking the Miller capacitance of the switching capacitor from generating overshoot or undershoot in the output differential voltage. Also, the output driver circuit may be driven by a differential skew cancellation circuit that generates a balanced differential signal to drive the switching transistors to further improve signal integrity. The signal path for generating each signal in the differential signal goes through a similar structure thereby ensuring similar slew in each differential signal provided to the output driver circuit.
1. A differential signal output driver circuit comprising:
a first voltage source;
a second voltage source;
a first bias terminal;
a second bias terminal;
a first switching terminal;
a second switching terminal;
a first output terminal;
a second output terminal;
a first switching field effect transistor having a source terminal coupled to the first voltage source, a gate terminal coupled to the second switching terminal, and a drain terminal;
a second switching field effect transistor having a source terminal coupled to the first voltage source, a gate terminal coupled to the first switching terminal, and a drain terminal;
a first bias field effect transistor having a source terminal coupled to the drain terminal of the first switching field effect transistor, a gate terminal coupled to the first bias terminal, and a drain terminal coupled to the first output terminal;
a second bias field effect transistor having a source terminal coupled to the drain terminal of the second switching field effect transistor, a gate terminal coupled to the first bias terminal, and a drain terminal coupled to the second output terminal;
a resistor coupled between the first output terminal and the second output terminal;
a third switching field effect transistor having a source terminal coupled at least indirectly to the second voltage source, a gate terminal coupled to the second switching terminal, and a drain terminal coupled at least indirectly to the drain terminal of the first bias field effect transistor; and
a fourth switching field effect transistor having a source terminal coupled at least indirectly to the second voltage source, a gate terminal coupled to the first switching terminal, and a drain terminal coupled at least indirectly to the drain terminal of the second bias field effect transistor.
2. A differential signal output driver circuit in accordance with claim 1 ,
wherein the first voltage source is configured during operation to supply a higher voltage than the second voltage source,
wherein the first switching field effect transistor, the second switching field effect transistor, the first bias field effect transistor, and the second bias field effect transistor are p-type field effect transistors; and
wherein the third switching field effect transistor and the fourth switching field effect transistor are n-type field effect transistors.
3. A differential signal output driver circuit in accordance with claim 1 ,
wherein the first voltage source is configured during operation to supply a lower voltage than the second voltage source,
wherein the first switching field effect transistor, the second switching field effect transistor, the first bias field effect transistor, and the second bias field effect transistor are n-type field effect transistors; and
wherein the third switching field effect transistor and the fourth switching field effect transistor are p-type field effect transistors.
4. A differential signal output driver circuit in accordance with claim 1 , further comprising the following:
a third bias field effect transistor having a source terminal coupled to the second voltage source, a gate terminal coupled to the second bias terminal, and a drain terminal coupled to the source terminal of the third switching field effect transistor and to the source terminal of the fourth switching field effect transistor.
5. A differential signal output driver circuit in accordance with claim 4 ,
wherein the first voltage source is configured during operation to supply a higher voltage than the second voltage source,
wherein the first switching field effect transistor, the second switching field effect transistor, the first bias field effect transistor, and the second bias field effect transistor are p-type field effect transistors; and
wherein the third switching field effect transistor, the fourth switching field effect transistor, and the third bias field effect transistor are n-type field effect transistors.
6. A differential signal output driver circuit in accordance with claim 4 ,
wherein the first voltage source is configured during operation to supply a lower voltage than the second voltage source,
wherein the first switching field effect transistor, the second switching field effect transistor, the first bias field effect transistor, and the second bias field effect transistor are n-type field effect transistors; and
wherein the third switching field effect transistor, the fourth switching field effect transistor, and the third bias field effect transistor are p-type field effect transistors.
7. A differential signal output driver circuit in accordance with claim 1 , further comprising:
a third bias field effect transistor having a source terminal coupled to the drain terminal of the third switching field effect transistor, a gate terminal coupled to the second bias terminal, and a drain terminal coupled to the drain terminal of the first bias field effect transistor; and
a fourth bias field effect transistor having a source terminal coupled to the drain terminal of the fourth switching field effect transistor, a gate terminal coupled to the second bias terminal, and a drain terminal coupled to the drain terminal of the second bias field effect transistor.
8. A differential signal output driver circuit in accordance with claim 1 , wherein the resistor is a series resistor comprising a first resistor and a second resistor, further comprising:
a common mode voltage terminal coupled between the first and second resistors.
9. A differential signal output driver circuit in accordance with claim 1 , wherein the first voltage source is approximately 3.3 volts and the second voltage source is approximately ground.
10. A differential signal output driver circuit in accordance with claim 1 , wherein the first voltage source is approximately 2.5 volts and the second voltage source is approximately ground.
11. A differential signal output driver circuit in accordance with claim 1 , wherein the first voltage source is approximately ground and the second voltage source is approximately 3.3 volts.
12. A differential signal output driver circuit in accordance with claim 1 , wherein the first voltage source is approximately ground and the second voltage source is approximately 2.5 volts.
13. A differential signal output driver circuit in accordance with claim 1 , further comprising the following:
one or more input stage circuitry configured during operation to generate a differential signal on the first and second switching terminals.