Granted Patent B2

US 7,247,565 · App. 10/925,078 · Granted Jul 24, 2007

Abstract

Claims (17)

1. A method for fabricating a copper interconnect comprising:

employing a damascene process to form a first trench in a first insulating layer;

depositing a first barrier layer in the first trench;

depositing a first copper layer on the first barrier layer;

depositing a second barrier layer on the first copper layer;

depositing a second insulating layer on the first insulating layer and the second barrier layer;

forming a via hole in the second insulating layer;

employing a damascene process to form a second trench in the second insulating layer; and

forming a via and an upper copper interconnect by depositing a third barrier layer and a second copper layer on the second insulating layer.

2. A method as defined in claim 1 , wherein the first, the second and the third barrier layers are made of Ta/TaN.

3. A method as defined in claim 1 , wherein the first and the second insulating layers are made of silicon oxide.

4. A method as defined in claim 1 , wherein the first copper layer has a thickness between about 200 Å and about 300 Å.

5. A method as defined in claim 1 , further comprising:

planarizing the first copper layer, wherein planarizing the first copper layer forms a bottom copper interconnect; and

planarizing the first and second barrier layers, wherein planarizing the first and second barrier layers removes the first and second barrier layers from the top of the first insulating layer.

6. A method as defined in claim 5 , wherein planarizing the first copper layer comprises dishing the first copper layer.

7. A method as defined in claim 1 , wherein a bottom portion of the third barrier layer is formed in the second barrier layer.

Assignments (9)