IP Library Granted Patent US 7,015,569
Granted Patent B1
US 7,015,569 · App. 10/927,985 · Granted Mar 21, 2006

Method and apparatus for implementing a co-axial wire in a semiconductor chip

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,015,569
App. No.
10/927,985
Granted
Mar 21, 2006
Kind
B1
Abstract

A coaxial shield for a semiconductor chip includes: a top vertical shield wire formed in a top metal layer of a semiconductor chip wherein the top vertical shield wire has a selected length for providing a coaxial shield; a first side shield wire formed in an intermediate metal layer of the semiconductor chip; a first upper via formed in a first dielectric layer of the semiconductor chip that extends lengthwise parallel to the first side shield wire to electrically connect the first side shield wire to the top vertical shield wire along the selected length; a second side shield wire formed in the intermediate metal layer of the semiconductor chip having a length corresponding to the selected length wherein the second side shield wire extends lengthwise parallel to the first side shield wire; and a second upper via formed in the first dielectric layer that extends lengthwise parallel to the second side shield wire to electrically connect the second side shield wire to the top vertical shield wire along the length corresponding to the selected length.

Claims (46)

1. A coaxial shield for a semiconductor chip comprising:

a top vertical shield wire formed in a top metal layer of a semiconductor chip wherein the top vertical shield wire has a selected length for providing a coaxial shield;

a first side shield wire formed in an intermediate metal layer of the semiconductor chip;

a first upper via formed in a first dielectric layer of the semiconductor chip that extends lengthwise parallel to the first side shield wire to electrically connect the first side shield wire to the top vertical shield wire along the selected length;

a second side shield wire formed opposite the first side shield wire in the intermediate metal layer of the semiconductor chip having a length corresponding to the selected length wherein the second side shield wire extends lengthwise parallel to the first side shield wire; and

a second upper via formed in the first dielectric layer that extends lengthwise parallel to the second side shield wire to electrically connect the second side shield wire to the top vertical shield wire along the length corresponding to the selected length.

2. The coaxial shield of claim 1 further comprising:

a bottom vertical shield wire formed in a bottom metal layer of the semiconductor chip;

a first lower via formed in a second dielectric layer of the semiconductor chip that extends lengthwise parallel to the first side shield wire to electrically connect the first side shield wire to the bottom vertical shield wire along the selected length; and

a second lower via formed in the second dielectric layer that extends lengthwise parallel to the second side shield wire to electrically connect the second side shield wire to the bottom vertical shield wire along the length corresponding to the selected length.

3. The coaxial shield of claim 1 further comprising a signal wire formed in the intermediate metal layer between the first shield wire and the second shield wire.

4. The coaxial shield of claim 3 wherein the signal wire extends lengthwise parallel to the first shield wire along the selected length.

5. The coaxial shield of claim 1 further comprising:

a third side shield wire formed in an additional intermediate metal layer of the semiconductor chip wherein the third side shield wire extends lengthwise parallel to the first side shield wire along the selected length;

a first lower via formed in a second dielectric layer of the semiconductor chip that extends lengthwise parallel to the third side shield wire to electrically connect the third side shield wire to the first side shield wire along the selected length;

a fourth side shield wire formed in the additional intermediate metal layer of the semiconductor chip wherein the fourth side shield wire extends lengthwise parallel to the second side shield wire along the length corresponding to the selected length; and

a second lower via formed in the second dielectric layer that extends lengthwise parallel to the second side shield wire to electrically connect the fourth side shield wire to the second side shield wire along the length corresponding to the selected length.

6. The coaxial shield of claim 5 further comprising:

a bottom vertical shield wire formed in a bottom metal layer of the semiconductor chip;

a third lower via formed in a third dielectric layer of the semiconductor chip that extends lengthwise parallel to the third side shield wire to electrically connect the third side shield wire to the bottom vertical shield wire along the selected length; and

a fourth lower via formed in the third dielectric layer that extends lengthwise parallel to the fourth side shield wire to electrically connect the fourth side shield wire to the bottom vertical shield wire along the length corresponding to the selected length.

7. The coaxial shield of claim 5 further comprising a signal wire formed in the intermediate metal layer between the first shield wire and the second shield wire.

8. The coaxial shield of claim 7 wherein the signal wire extends lengthwise parallel to the first shield wire along the selected length.

9. A method of shielding a volume in a semiconductor chip comprising steps of:

forming a top vertical shield wire in a top metal layer of a semiconductor chip wherein the top vertical shield wire has a selected length for providing a coaxial shield;

forming a first side shield wire in an intermediate metal layer of the semiconductor chip;

forming a first upper via in a first dielectric layer of the semiconductor chip that extends lengthwise parallel to the first side shield wire to electrically connect the first side shield wire to the top vertical shield wire along the selected length;

forming a second side shield wire in the intermediate metal layer of the semiconductor chip having a length corresponding to the selected length wherein the second side shield wire extends lengthwise parallel to the first side shield wire; and

forming a second upper via in the first dielectric layer that extends lengthwise parallel to the second side shield wire to electrically connect the second side shield wire to the top vertical shield wire along the length corresponding to the selected length.

10. The method of claim 9 further comprising steps of:

forming a bottom vertical shield wire in a bottom metal layer of the semiconductor chip;

forming a first lower via in a second dielectric layer of the semiconductor chip that extends lengthwise parallel to the first side shield wire to electrically connect the first side shield wire to the bottom vertical shield wire along the selected length; and

forming a second lower via in the second dielectric layer that extends lengthwise parallel to the second side shield wire to electrically connect the second side shield wire to the bottom vertical shield wire along the length corresponding to the selected length.

11. The method of claim 9 further comprising a step of forming a signal wire in the intermediate metal layer between the first shield wire and the second shield wire.

12. The method of claim 11 wherein the signal wire extends lengthwise parallel to the first shield wire along the selected length.

13. The method of claim 9 further comprising a steps of:

forming a third side shield wire in an additional intermediate metal layer of the semiconductor chip wherein the third side shield wire extends lengthwise parallel to the first side shield wire along the selected length;

forming a first lower via in a second dielectric layer of the semiconductor chip that extends lengthwise parallel to the third side shield wire to electrically connect the third side shield wire to the first side shield wire along the selected length;

forming a fourth side shield wire in the additional intermediate metal layer of the semiconductor chip wherein the fourth side shield wire extends lengthwise parallel to the second side shield wire along the length corresponding to the selected length; and

forming a second lower via in the second dielectric layer that extends lengthwise parallel to the second side shield wire to electrically connect the fourth side shield wire to the second side shield wire along the length corresponding to the selected length.

14. The method of claim 13 further comprising steps of:

forming a bottom vertical shield wire in a bottom metal layer of the semiconductor chip;

forming a third lower via in a third dielectric layer of the semiconductor chip that extends lengthwise parallel to the third side shield wire to electrically connect the third side shield wire to the bottom vertical shield wire along the selected length; and

forming a fourth lower via in the third dielectric layer that extends lengthwise parallel to the fourth side shield wire to electrically connect the fourth side shield wire to the bottom vertical shield wire along the length corresponding to the selected length.

15. The method of claim 13 further comprising forming a signal wire in the intermediate metal layer between the first shield wire and the second shield wire.

16. The method of claim 15 wherein the signal wire extends lengthwise parallel to the first shield wire along the selected length.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0719 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0608 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
CHANGE OF NAME Recorded Jun 6, 2014
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 033102/0270 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →