Semiconductor contact and nitride spacer formation system and method
View Patent ↗The present invention is a semiconductor contact formation system and methods that form contact insulation regions comprising multiple etch stop sublayers that facilitate formation of contacts. This contract formation process provides relatively small substrate connections while addressing critical lithographic printing limitation concerns in forming contact holes with small dimensions. In one embodiment, a multiple etch stop contact formation process in which a multiple etch stop insulation layer comprising multiple etch stop layers is deposited. A contact region is formed in the multiple etch stop insulation layer by selectively removing (e.g., etching) some of the multiple etch stop insulation layer. In one embodiment a larger portion of the multiple etch stop insulation layer is removed close to the metal layer and a smaller portion is removed closer to the substrate. The different contact region width are achieved by performing multiple etching processes controlled by the multiple etch stop layers in the multiple etch stop insulation layer and spacer formation to shrink contact size at a bottom portion. Electrical conducting material (e.g., tungsten) is deposited in the contact region.
1. A contact formation process comprising;
preparing a silicon wafer substrate;
forming a gate region;
creating source and drain regions;
depositing a multiple etch stop insulation layer comprising multiple etch stop layers;
forming a contact region in said multiple etch stop insulation layer by selectively removing some of said multiple etch stop insulation layer and forming at least one sub spacer such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region; and
depositing an electrical conducting material in said contact region.
2. A contact formation process of claim 1 wherein
the at least one sub spacer comprises nitride.
3. A contact formation process of claim 2 wherein said depositing said multiple etch stop insulation layer comprises:
depositing a first etch stop layer;
depositing a first sub interlevel dielectric layer;
depositing a second etch stop layer, and
depositing a second sub interlevel dielectric layer.
4. A contact formation process of claim 3 further comprising depositing an ARC (anti-reflective coating) layer.
5. A contact formation process of claim 3 , wherein said selectively removing some of said multiple etch stop insulation layer further comprises:
etching away a portion of said second sub interlevel dielectric layer;
removing a portion of said second etch stop layer;
depositing a spacer dielectric material and etching to form said at least one sub spacer;
etching away a portion of said first sub interlevel dielectric layer; and
removing a portion of said first etch stop layer.
6. A contact formation process of claim 2 wherein said substrate coupling area of said contact region ranges between 0.06 micro-meter and 0.13 micro-meter; and wherein said metal layer coupling area of said contact region ranges between 0.16 micro-meter and 0.18 micro-meter.
7. A contact formation process of claim 1 wherein said preparing silicon comprises:
planarizing said silicon wafer substrate;
depositing an oxide pad layer;
depositing a nitride protective layer; and
polishing said nitride protective layer.
8. A contact formation process of claim 1 wherein said forming said gate region comprises:
depositing a gate insulation layer;
depositing a control gate layer; and
removing said gate insulation layer and said control gate layer from non gate region areas.
9. A contact formation process of claim 8 further comprising forming a floating gate.
10. A contact formation process of claim 1 wherein said creating source and drain regions comprises introducing dopants into said silicon wafer substrate.
11. A contact formation process comprising:
depositing a multiple etch stop insulation layer comprising multiple etch stop layers;
forming a contact region in said multiple etch stop insulation layer by selectively removing some of said multiple etch stop insulation layer and forming at least one sub spacer such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region; and
depositing a conducting material in said contact region.
12. A contact formation process of claim 11 wherein said depositing said multiple etch stop insulation layer comprises:
depositing a first etch stop layer;
depositing a first sub interlevel dielectric layer;
depositing a second etch stop layer, and
depositing a second sub interlevel dielectric layer.
13. A contact formation process of claim 12 wherein said selectively removing some of said multiple etch stop insulation layer further comprises:
etching away a portion of said second sub interlevel dielectric layer;
removing a portion of said second etch stop layer;
depositing a spacer dielectric material and etching to form said at least one sub spacer;
etching away a portion of said first sub interlevel dielectric layer; and
removing a portion of said first etch stop layer.
14. A contact formation process of claim 13 wherein said first etch stop layer and second etch stop layer comprise nitride.
15. A contact formation process of claim 13 wherein said at least one sub spacer comprises nitride and SiON.
16. A contact formation process of claim 11 wherein said forming said contact region is performed by a lithography process combined with a non-lithography spacer formation process to achieve a sub-100 micro-meter contact bottom dimension.