IP Library Granted Patent US 7,023,188
Granted Patent B1
US 7,023,188 · App. 10/937,684 · Granted Apr 4, 2006

Method of forming a multi-phase power supply controller

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Quick Facts
Patent No.
US 7,023,188
App. No.
10/937,684
Granted
Apr 4, 2006
Kind
B1
Abstract

In one embodiment, a power supply controller has a plurality of PWM control channels. The PWM control signals of the PWM control channels are selectively alternated among the outputs of the power supply controller.

Claims (29)

1. A method of forming a power controller comprising:

forming the power controller to include at least a first PWM controller, a second PWM controller, a first PWM output operable for coupling to a first power stage, and a second PWM output operable for coupling to a second power stage;

configuring the power controller to selectively use a first PWM control signal from the first PWM controller to control a first PWM drive signal on the first PWM output for a first time period; and

configuring the power controller to selectively use the first PWM control signal from the first PWM controller to control a second PWM drive signal on the second PWM output for a second time period.

2. The method of claim 1 wherein configuring the power controller to selectively use the first PWM control signal from the first PWM controller to control the first PWM drive signal on the first PWM output for the first time period includes configuring the power controller to selectively use a second PWM control signal from the second PWM controller to control the second PWM drive signal on the second PWM output.

3. The method of claim 1 wherein configuring the power controller to selectively use the first PWM control signal from the first PWM controller to control the second PWM drive signal on the second PWM output for the second time period includes configuring the power controller to selectively use a second PWM control signal from the second PWM controller to control the second PWM drive signal on the first PWM output.

4. The method of claim 1 wherein forming the power controller to include at least the first PWM controller, the second PWM controller, and the first PWM output includes configuring the power controller to include more PWM controllers than PWM outputs.

5. The method of claim 1 further including configuring the power controller to selectively use a second PWM control signal from the second PWM controller to control the second PWM drive signal on the first PWM output during a third time period and to use a third PWM control signal from a third PWM controller to control a third PWM drive signal on a third PWM output during a fourth time period.

6. The method of claim 5 further including configuring the power controller to form the third time period and the fourth time period between the first time period and the second time-period.

7. The method of claim 5 further including configuring the power controller to form the third time period after the second time period and the fourth time period after the third time period.

8. A method of controlling a power supply comprising:

using a first PWM control signal from a first PWM controller to control a first power switch of the power supply for a first time period;

using a second PWM control signal from a second PWM controller to control a second power switch of the power supply; and

using the first PWM control signal from the first PWM controller to control the second power switch for a second time period.

9. The method of claim 8 wherein using the second PWM signal from the second PWM controller to control the second power switch includes using the second PWM control signal from the second PWM controller to control the second power switch after the first time period.

10. The method of claim 8 wherein using the first PWM control signal from the first PWM controller to control the second power switch for the second time period includes using the second PWM control signal from the second PWM controller to control a third power switch for a third time period that is after the second time period.

11. The method of claim 10 further including using a third PWM control signal from a third PWM controller to control the first power switch for a third time period that is after the second time period.

12. The method of claim 8 wherein using the first PWM control signal from the first PWM controller to control the second power switch for the second time period includes using the second PWM control signal from the second PWM controller to control the first power switch after the second time period.

13. The method of claim 8 further including using a first plurality of power switches and a second plurality of PWM control signals wherein the second plurality is larger than the first plurality, and periodically selecting a PWM control signal of the second plurality of PWM control signals to couple to a power switch of the first plurality of power switches.

14. A power supply controller comprising:

a first plurality of PWM drive outputs;

a second plurality of PWM controllers, each PWM controller operable to generate a PWM control signal; and

a control circuit operable to selectively couple a first PWM control signal to control a first PWM drive output of the first plurality of PWM drive outputs during a first time period and to couple the first PWM control signal to control a second PWM drive output of the first plurality of PWM drive outputs during a second time period.

15. The power supply controller of claim 14 further including the control circuit operable to selectively couple a second PWM control signal to control the second PWM drive output of the first plurality of PWM drive outputs during a third time period and to couple a third PWM control signal to control a third PWM drive output of the first plurality of PWM drive outputs during a fourth time period.

16. The power supply controller of claim 15 wherein the third time period occurs after the second time period and the fourth time period occurs after the third time period.

17. The power supply controller of claim 15 wherein the third time period and the fourth time period occur between the first time period and the second time period.

18. The power supply controller of claim 15 wherein the second plurality of PWM controllers is greater than the first plurality of PWM drive outputs.

19. The power supply controller of claim 15 wherein the control circuit de-couples a second PWM control signal from a second PWM controller of the second plurality of PWM controllers from controlling any PWM drive output of the first plurality of PWM drive outputs during the first time period.

20. The power supply controller of claim 15 wherein the control circuit couples a second PWM control signal from a second PWM controller of the second plurality of PWM controllers to control the second PWM drive output during the first time period.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT AND COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038631/0345 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: JPMORGAN CHASE BANK, N.A. (ON ITS BEHALF AND ON BEHALF OF ITS PREDECESSOR IN INTEREST, CHASE MANHATTAN BANK)
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038632/0074 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2005
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 016183/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 10, 2004
From: RICE, BENJAMIN M.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, L.L.C.
Reel/Frame 015782/0409 →