IP Library Granted Patent US 7,432,157
Granted Patent B2
US 7,432,157 · App. 10/950,218 · Granted Oct 7, 2008

Method of fabricating flash memory

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Quick Facts
Patent No.
US 7,432,157
App. No.
10/950,218
Granted
Oct 7, 2008
Kind
B2
Abstract

Flash memory and methods of fabricating flash memory are disclosed. A disclosed method comprises: forming a first floating gate; and extending the first floating gate by forming a second floating gate adjacent a first sidewall of the floating gate. The second floating gate extends upward above the first floating gate. The method also includes depositing a dielectric layer on the first floating gate and the second floating gate; and forming a control gate on the dielectric layer.

Claims (11)

1. A method of fabricating a flash memory comprising:

forming a first floating gate;

extending the first floating gate by forming a step-shaped second floating gate adjacent a first sidewall of the first floating gate, the step-shaped second floating gate including a first part extending upward above the first floating gate and a second part extending sideward from the first part, wherein forming the step-shaped second floating gate adjacent the first sidewall of the first floating gate comprises:

depositing a polysilicon layer over the first floating gate;

forming spacers on side-wall portions of the polysilicon layer, wherein the spacers are in contact with the side-wall portions and an upper surface of the polysilicon layer below the spacers; and

etching the polysilicon layer using the spacers as a mask to form the step-shaped second floating gate;

depositing a dielectric layer on the first floating gate and the step-shaped second floating gate, wherein the dielectric layer is in contact with both the first floating gate and the step-shaped second floating gate; and

forming a control gate on the dielectric layer.

2. A method as defined in claim 1 wherein the step-shaped second floating gate does not extend over the first floating gate.

3. A method as defined in claim 1 wherein the step-shaped second floating gate is located above a first STI area adjacent the first floating gate.

4. A method as defined in claim 3 , wherein the second part of the step-shaped second floating gate is in contact with the first STI area.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 28, 2014
From: DONGBU HITEK CO., LTD.
To: DSS TECHNOLOGY MANAGEMENT, INC.
Reel/Frame 033035/0680 →
CHANGE OF NAME Recorded Jun 6, 2006
From: DONGBU ANAM SEMICONDUCTORS, INC
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017718/0964 →
MERGER Recorded May 31, 2005
From: DONGBU SEMICONDUCTOR INC.
To: DONGBUANAM SEMICONDUCTOR, INC.
Reel/Frame 016593/0667 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 24, 2004
From: KIM, BONG KIL
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 015834/0994 →