Semiconductor devices having a capacitor and methods of manufacturing the same
View Patent ↗Semiconductor devices having a capacitor and methods of manufacturing the same are disclosed. A disclosed semiconductor device includes a semiconductor substrate; a lower interconnection line on the substrate; an upper interconnection line electrically connected to a first portion of the lower interconnection line; a first metal layer electrically connected to a second portion of the lower interconnection line; a capacitor insulating layer on the first metal layer; and a second metal layer on the capacitor insulating layer, wherein the first metal layer, the capacitor insulating layer and the second metal layer form a capacitor
1. A method of manufacturing a semiconductor device comprising:
sequentially forming first, second, and third insulating layers on a semiconductor substrate having a lower interconnection line thereon;
etching the third insulating layer to form an insulating layer pattern having (i) a first space exposing a first portion of the second insulating layer over a first portion of the lower interconnection line and (ii) a second space exposing a second portion of the second insulating layer over a second portion of the lower interconnection line;
forming a fourth insulating layer on the insulating layer pattern including in the first and second spaces;
etching the fourth insulating layer using the insulating layer pattern as an etch barrier to form a first trench and a second trench;
etching the first and second insulating layers to form a first via hole exposing the first portion of the lower interconnection line and a second via hole exposing the second portion of the lower interconnection line;
forming a first metal layer on an entire surface of the device;
forming a capacitor insulating layer on the first metal layer in the second via hole and the second trench;
forming a second metal layer on an entire surface of the device including in the first and second via holes and first and second trenches; and
planarizing the second metal layer to expose the fourth insulating layer and form an upper interconnection line on the first portion of the lower interconnection line and a capacitor on the second portion of the lower interconnection line.
2. A method as defined in claim 1 , wherein the first and second trenches have a curved profile.
3. A method as defined in claim 2 , wherein etching the fourth insulating layer comprises a wet etching process.
4. The method of claim 1 , wherein etching the insulating layers comprises forming an organic antireflective coating (ARC) layer on the insulating layer prior to forming a photoresist pattern.
5. A method as defined in claim 1 , wherein etching the first, second, and third insulating layers comprises a dry etching process.
6. The method as defined in claim 1 , wherein etching the capacitor insulating layer comprises a wet etching process.
7. The method of claim 1 , wherein the capacitor insulating material layer has a uniform thickness.
8. A method of manufacturing a semiconductor device comprising:
sequentially forming first, second, and third insulating layers on a semiconductor substrate having a lower interconnection line thereon;
etching the third insulating layer to form an insulating layer pattern having (i) a first space exposing a first portion of the second insulating layer over a first portion of the lower interconnection line and (ii) a second space exposing a second portion of the second insulating layer over a second portion of the lower interconnection line;
forming a fourth insulating layer on the insulating layer pattern including in the first and second spaces;
etching the fourth insulating layer using the insulating layer pattern as an etch barrier to form a first trench and a second trench;
etching the first and second insulating layers to form a first via hole exposing the first portion of the lower interconnection line and a second via hole exposing the second portion of the lower interconnection line;
forming a capacitor insulating layer on the second via hole and the second trench;
forming a metal layer on an entire surface of the device, including in the first and second via holes and first and second trenches; and
planarizing the second metal layer to expose the fourth insulating layer and form an upper interconnection line on the first portion of the lower interconnection line and a capacitor including the lower interconnection line on the second portion of the lower interconnection line.
9. A method as defined in claim 8 , further comprising etching the insulating layer pattern and the first and second insulating layers at sides of the second via hole to widen the second via hole after forming the second via hole and before forming the capacitor insulating layer.
10. A method as defined in claim 9 , wherein the second via hole and the second trench have a substantially identical width.
11. A method as defined in claim 8 , further comprising forming a barrier metal layer after forming the capacitor insulating layer end before forming the metal layer.
12. The method of claim 8 , wherein etching the insulating layer comprises forming an organic antireflective coating (ARC) layer on the insulating layer prior to forming a photoresist pattern.
13. A method as defined in claim 8 , wherein etching the first, second, and third insulating layers comprises a dry etching process.
14. The method as defined in claim 8 , wherein etching the capacitor insulating layer comprises a wet etching process.
15. The method of claim 8 , wherein the capacitor insulating material layer has a uniform thickness.