Method of forming a low thermal resistance device and structure
View Patent ↗A semiconductor device is formed to have a shape that reduces the thermal resistance of the semiconductor device.
1. A method of forming a semiconductor device comprising:
forming doped regions of the semiconductor device in a device shape having a first perimeter that has a first length on a surface of a semiconductor substrate and having a first area; and
arranging the doped regions to form the device shape that is a four sided polygon wherein the first length is approximately 1.8 to 2.4 times a first distance around a circumference of a circle having the first area.
2. The method of claim 1 wherein forming doped regions of the semiconductor device in the device shape having the first perimeter that has the first length on the surface of the semiconductor substrate and having the first area includes coupling together a plurality of cells to function substantially in unison to form a functionality for the semiconductor device.
3. The method of claim 2 wherein coupling together the plurality of cells to function substantially in unison includes coupling together the plurality of cells to function substantially in unison wherein a line connecting an outer side of doped regions of the plurality of cells forms the device shape.
4. The method of claim 2 wherein coupling together the plurality of cells to function substantially in unison to form the functionality for the semiconductor device includes coupling together the plurality of cells wherein each cell has a first current carrying electrode and a second current carrying electrode wherein all first current carrying electrodes are commonly connected together and all second current carrying electrodes are commonly connected together.
5. The method of claim 2 further including each cell having a control electrode wherein all control electrodes are commonly connected together.
6. The method of claim 1 wherein forming doped regions of the semiconductor device in the device shape having the first perimeter that has the first length on the surface of the semiconductor substrate and having the first area includes coupling together a plurality of cells wherein a line intersecting a distal edge of doped regions of a current carrying electrode of the plurality cells forms at least one side of the first perimeter.
7. The method of claim 1 wherein arranging the doped regions to form the device shape includes arranging the doped regions to form the device shape as one of a rectangle, parallelogram, trapezoid, or rhombus.
8. The method of claim 1 wherein forming the doped regions of the semiconductor device includes forming the doped regions of one of a lateral power transistor or a vertical power transistor.
9. The method of claim 1 wherein arranging the doped regions includes arranging a source region or a drain region wherein one side of the source region or the drain region forms a side of the first perimeter.
10. A method of improving the thermal dissipation of a semiconductor device comprising:
arranging doped regions of the semiconductor device to form a device shape having a first perimeter having a first length and a first area wherein the device shape is a four sided polygon wherein the first length is about 1.8 to 2.4 times a first distance around a circumference of a circle having the first area.
11. The method of claim 10 wherein arranging the doped regions includes arranging a plurality of device cells to form the device shape.
12. The method of claim 10 wherein arranging the doped regions includes arranging the doped regions of the semiconductor device to form the device shape that is one of a rectangle, parallelogram, trapezoid, or rhombus.
13. A semiconductor device comprising:
a device shape having a first perimeter having a first length and a first area wherein the device shape is a four sided polygon wherein the first length is about 1.8 to 2.4 times a first distance around a circumference of a circle having the first area.
14. The semiconductor device of claim 13 wherein the device shape includes a plurality of cells operably coupled to function substantially in unison to form a functionality for the semiconductor device.
15. The semiconductor device of claim 14 wherein outer sides of doped regions of the plurality of cells form the device shape.
16. The semiconductor device of claim 13 further including a line intersecting a distal edge of doped regions of a current carrying electrode of the semiconductor device forming at least one side of the first perimeter.
17. The semiconductor device of claim 13 wherein the semiconductor device is one of a lateral transistor or a vertical transistor.
18. The semiconductor device of claim 13 wherein the device shape is one of a rectangle, parallelogram, trapezoid, or rhombus.