Flash memory device having increased over-erase correction efficiency and robustness against device variations
View Patent ↗A memory device is provided including circuitry for correcting an over-erased memory cell in the memory device. The memory device may include a substrate. A control gate and a floating gate may be formed over the substrate. The memory device may include a source region and a drain region. A first resistive element may be coupled between the source region and the control gate.
1. A memory device including circuitry for correcting an over-erased memory cell in the memory device, comprising:
a substrate;
a control gate and a floating gate formed over the substrate;
a source region and a drain region;
a first resistor coupled between the source region and a node,
where the node is coupled to the control gate; and
a second resistor coupled between the node and a ground terminal.
2. The memory device of claim 1 , further comprising:
a terminal coupled to the second resistor, the terminal to receive a voltage from a voltage source.
3. The memory device of claim 1 , where the first resistor and the second resistor have resistance values ranging from about 1 kΩ to about 50 kΩ.
4. The memory device of claim 1 , where:
the first resistor has a resistance value of about 6 kΩ; and
the second resistor has a resistance value of about 3 kΩ.
5. The memory device of claim 2 , where the voltage source applies a voltage ranging from about 0.3 volts to about 1.0 volts.
6. The memory device of claim 5 , where the voltage source applies a voltage of about 0.5 volts.
7. The memory device of claim 1 , where the memory device includes a plurality of memory cells comprised of N-channel field effect transistors.
8. A memory device including circuitry for correcting an over-erased memory cell in the memory device, comprising:
a substrate;
a control gate and a floating gate formed over the substrate;
a control gate terminal coupled to the control gate;
a source region and a drain region;
a source terminal coupled to the source region; and
a first resistor coupled between the source terminal and a second terminal,
where the second terminal is directly coupled to the control gate terminal, and where the second terminal is to directly receive a voltage from a voltage source, where the voltage applied to the second terminal is not applied to the first resistor before reaching the second terminal.
9. The memory device of claim 8 , where the voltage source applies a voltage ranging from about 0.3 volts to about 1.0 volts.
10. The memory device of claim 9 , where the voltage source applies a voltage of about 0.7 volts.
11. The memory device of claim 8 , where the first resistor has a resistance value of about 4 kΩ.
12. A method for performing an automatic program disturb after erase (APDE) process for correcting an over-erased memory cell having a substrate, a control gate and a floating gate formed over the substrate, and a source region and a drain region, comprising:
applying a first voltage to the control gate;
applying a second voltage to the source region, the second voltage being different than the first voltage;
coupling a first resistor between the source region and the control gate; and
coupling a second resistor between the first resistor and a ground terminal.
13. The method of claim 12 , where:
the first resistor has a resistance value of about 6 kΩ; and
the second resistor has a resistance value of about 3 kΩ.
14. A method for performing an automatic program disturb after erase (APDE) process for correcting an over-erased memory cell having a substrate, a control gate and a floating gate formed over the substrate, and a source region and a drain region, comprising:
applying a first voltage to the control gate;
applying a second voltage to the source region, the second voltage being different than the first voltage;
coupling a first resistor between the source region and the control gate; and
coupling a second resistor between the first resistor and a terminal, the terminal to receive a voltage from a voltage source.
15. A method for performing an automatic program disturb after erase (APDE) process for correcting an over-erased memory cell having a substrate, a control gate and a floating gate formed over the substrate, and a source region and a drain region, comprising:
applying a first voltage to the control gate;
applying a second voltage to the source region, the second voltage being different than the first voltage;
coupling a first resistor between the source region and a terminal; and
coupling the terminal to the control gate, the terminal to receive a voltage from a voltage source, where the voltage applied to the terminal is not applied to the first resistor before reaching the terminal.
16. The method of claim 15 , where the voltage source applies a voltage ranging from about 0.3 volts to about 1.0 volts.
17. A memory device, comprising:
a plurality of memory cells arranged in a column;
each of the plurality of memory cells comprising:
a substrate, where a first portion of the substrate acts as a source region for the memory cell and a second portion of the substrate acts as a drain region for the memory cell;
a first dielectric layer formed on the substrate; and
a stacked gate structure formed on the first dielectric layer, the stacked gate structure including a floating gate and a control gate separated by a second dielectric layer,
where drain region for each of the plurality of memory cells is coupled to a common bit line terminal,
where source region for each of the plurality of memory cells is coupled to a common source terminal,
where the control gate for each of the plurality of memory cells is coupled to a control gate terminal,
where the substrate for each of the plurality of memory cells is coupled to a common substrate terminal;
a first resistor coupled between the common source terminal and the control gate terminal; and
a second resistor coupled between the first resistor and a ground terminal.
18. The memory device of claim 17 , where:
the first resistor has a resistance value of about 6 kΩ; and
the second resistor has a resistance value of about 3 kΩ.