Semiconductor device and manufacturing method thereof
View Patent ↗The semiconductor device fabrication method of the present invention includes forming metal wirings on a semiconductor substrate, forming a first blocking layer on the semiconductor substrate and the metal wiring, forming a first FSG on the first blocking layer, forming a second blocking layer on the first FSG, forming a second FSG on the second blocking layer, and forming a protection layer on the second FSG.
1. A semiconductor device comprising:
a semiconductor substrate;
metal wirings on the semiconductor substrate;
a first blocking layer comprising USG, covering the semiconductor substrate and the metal wirings, contacting side walls of the metal wirings, and filling a gap between the metal wirings;
a FSG layer on the first blocking layer;
a second blocking layer comprising USG on the FSG layer;
an inter-metal dielectric layer comprising FSG on the second blocking layer; and
a protection layer on the inter-metal dielectric layer.
2. The semiconductor device of claim 1 , wherein the first and the second blocking layers have a thickness in the range from 30 to 2000 Å.
3. The semiconductor device of claim 1 further comprising a third blocking layer on the inter-metal dielectric layer and a second inter-metal dielectric layer on the third blocking layer.
4. The semiconductor device of claim 3 , wherein the second inter-metal dielectric layer comprises FSG.
5. The semiconductor device of claim 1 , comprising a planar protection layer.
6. The semiconductor device of claim 5 , further comprising a wiring layer on the protection layer.
7. The semiconductor device of claim 6 , wherein the wiring layer connects to the metal wirings through contacts.
8. The semiconductor device of claim 3 , comprising a planar protection layer.
9. The semiconductor device of claim 8 , further comprising a wiring layer on the protection layer.
10. The semiconductor device of claim 9 , wherein the wiring layer connects to the metal wirings through contacts.
11. The semiconductor device of claim 2 , further comprising a third blocking layer on the inter-metal dielectric layer and a second inter-metal dielectric layer on the third blocking layer.
12. The semiconductor device of claim 11 , wherein the second inter-metal dielectric layer comprises FSG.
13. The semiconductor device of claim 12 , comprising a planar protection layer.
14. The semiconductor device of claim 13 , further comprising a wiring layer on the protection layer.
15. The semiconductor device of claim 14 , wherein the wiring layer connects to the metal wirings through contact.
16. The semiconductor device of claim 1 , wherein the gap between the metal wirings is further filled with the FSG layer.
17. The semiconductor device of claim 1 , wherein the gap between the metal wirings is further filled with the second blocking layer.
18. The semiconductor device of claim 1 , wherein the gap between the metal wirings is further filled with the inter-metal dielectric layer.