Lateral trench field-effect transistors in wide bandgap semiconductor materials, methods of making, and integrated circuits incorporating the transistors
View Patent ↗A junction field effect transistor is described. The transistor is made from a wide bandgap semiconductor material. The device comprises source, channel, drift and drain semiconductor layers, as well as p-type implanted or Schottky gate regions. The source, channel, drift and drain layers can be epitaxially grown. The ohmic contacts to the source, gate, and drain regions can be formed on the same side of the wafer. The devices can have different threshold voltages depending on the vertical channel width and can be implemented for both depletion and enhanced modes of operation for the same channel doping. The devices can be used for digital, analog, and monolithic microwave integrated circuits. Methods for making the transistors and integrated circuits comprising the devices are also described.
1. A junction field-effect transistor comprising:
a substrate having opposed first and second major surfaces;
a drain layer of an n-type semiconductor material on the first major surface of the substrate;
a drift layer of an n-type semiconductor material on and non-coextensive with the drain layer such that portions of the drain layer are exposed, the drift layer having a lower conductivity than the drain layer;
one or more discrete raised regions in spaced relation on the drain layer, each of the raised regions comprising a channel region of an n-type semiconductor material on the drift layer and a source region of an n-type semiconductor material on the channel region, the material of the source region having a higher conductivity than that of the channel region;
a gate region of a p-type semiconductor material on the drift layer adjacent the one or more raised regions and forming a rectifying junction with n-type material of the drift layer and the channel region(s); and
ohmic contacts on the gate and source regions and on exposed portions of the drain layer.
2. The junction field-effect transistor of claim 1 , wherein the semiconductor material of the drain layer, drift layer, gate region, channel region and source region has an E G of at least 2 eV.
3. The junction field-effect transistor of claim 1 , wherein the source region is coextensive with the channel region.
4. The junction field-effect transistor of claim 1 , comprising a plurality of raised regions, wherein each of the raised regions is elongate having a major and a minor dimension and wherein the major dimensions of the raised regions are oriented parallel to one another.
5. The junction field-effect transistor of claim 4 , wherein the plurality of raised source regions are spaced apart from one another at regular intervals in the direction of the minor dimension.
6. The junction field-effect transistor of claim 5 , wherein the gate region comprises a plurality of fingers extending between adjacent raised regions.
7. The junction field-effect transistor of claim 1 , wherein the substrate is selected from the group consisting of: semi-insulating; p-type; or n-type with a p-type buffer layer thereon wherein the p-type buffer layer forms the first major surface of the substrate.
8. The junction field-effect transistor of claim 2 , wherein the semiconductor material of each of the drain layer, drift layer, gate region, channel region and source region is SiC.
9. The junction field-effect transistor of claim 2 , wherein the semiconductor material of each of the drain layer, drift layer, gate region, channel region and source region is a Group III nitride compound semiconductor material.
10. A field-effect transistor comprising:
a substrate having opposed first and second major surfaces;
a drain layer of an n-type semiconductor material on the first major surface of the substrate; and
a drift layer of an n-type semiconductor material on the drain layer and non-coextensive therewith such that portions of the drain layer are exposed, the drift layer having a lower conductivity than the drain layer;
a gate region of a p-type semiconductor material formed in the drift layer;
a channel region of an n-type semiconductor material on the drift layer and forming a rectifying junction with the gate region; and
a source region of an n-type semiconductor material on the channel region, the semiconductor material of the source region having a higher conductivity than that of the channel region; and
ohmic contacts on the source region and on exposed portions of the drain layer.
11. The field-effect transistor of claim 10 , wherein the source and channel regions and the drift layer are coextensive.
12. The field-effect transistor of claim 10 , wherein the gate region comprises a plurality of fingers.