Granted Patent B2

US 7,186,641 · App. 11/009,470 · Granted Mar 6, 2007

Abstract

Claims (17)

1. A method of forming a metal interconnection line for a semiconductor device, the method comprising:

forming a first metal layer on a semiconductor substrate;

forming a second metal layer comprising aluminum, aluminum alloy, copper, tungsten, or a metal silicide layer on the first metal layer.

forming plugs by patterning the second metal layer;

forming a glue layer comprising Ti, Ti/TiN, Ta, or Ta/TaN to cover surfaces of the plugs;

forming lower metal interconnection lines by patterning the first metal layer, wherein forming the lower metal interconnection lines comprises:

forming a mask pattern having larger width than that of the plug on the first metal layer to cover the plugs;

etching the first metal layer using the mask pattern and plugs; and

removing the mask pattern; and

forming an interlayer insulating layer having a planarized surface on the substrate to fill gaps between the lower metal lines and between the plugs.

2. The method as defined by claim 1 , further comprising forming barrier metal layers on upper and lower portions of the first metal layer.

3. The method as defined by claim 2 , wherein the barrier metal layers comprise Ti, Ti/TiN, Ta,or Ta/TaN layers.

4. The method as defined by claim 1 , further comprising:

forming a third metal layer on the entire substrate; and

forming upper metal interconnection lines to be connected to the lower metal interconnection lines via plugs by patterning the third metal layer.

5. The method as defined by claim 4 , further comprising forming barrier metal layers on upper and lower portions of the third metal layer.

6. The method as defined by claim 5 , wherein the barrier metal layers comprise Ti, Ti/TiN, Ta, or Ta/TaN layers.

Assignments (10)