Interface system and method therefor
View Patent ↗In one embodiment, a differential transistor pair of an ECL differential amplifier is formed on two different semiconductor die.
1. An interface system comprising:
a first semiconductor device having a transmitter device;
a first voltage follower of the transmitter device having a first current carrying electrode coupled to receive a first power supply voltage, and a second current carrying electrode coupled to an output terminal of the first semiconductor device;
a second semiconductor device having a receiver device; and
a cascode transistor of the second semiconductor device having a first current carrying electrode coupled to receive a second power supply voltage, and a second current carrying electrode coupled to an input terminal of the receiver device wherein the cascode transistor is devoid of an active pull-down.
2. The interface system of claim 1 wherein the transmitter device is formed on a first semiconductor die and the receiver device is formed on a second semiconductor die.
3. The interface system of claim 1 wherein the first voltage follower is an emitter follower and the cascode transistor is configured as a common base.
4. The interface system of claim 1 wherein the first voltage follower is devoid of an active pull-down device coupled to the second current carrying electrode.
5. The interface system of claim 1 wherein the first voltage follower is a source follower.
6. The interface system of claim 1 further including a termination resistor coupled to the second current carrying electrode of the cascade transistor.
7. The interface system of claim 1 wherein a control electrode of the first voltage follower is coupled to receive a signal to be transmitted to the receiver device.
8. A method of forming a differential amplifier comprising:
forming a first transistor of a differential pair as a portion of a first semiconductor device; and
configuring the first transistor to receive a signal from a second transistor of the differential pair that is external to the first semiconductor device wherein a first current carrying electrode of the first transistor is devoid of a coupling to an active pull-down device.
9. The method of claim 8 wherein configuring the first transistor to receive the signal from the second transistor includes forming the second transistor on a second semiconductor device.
10. The method of claim 8 wherein forming the first transistor of the differential pair as the portion of the first semiconductor device includes forming the first semiconductor device on a first semiconductor die.
11. The method of claim 10 wherein configuring the first transistor to receive the signal from the second transistor includes forming the second transistor on a second semiconductor die.
12. The method of claim 8 wherein configuring the first transistor to receive the signal from the second transistor includes coupling a termination resistor to a first current carrying electrode of the first transistor.
13. The method of claim 8 wherein configuring the first transistor to receive the signal from the second transistor includes coupling the first current carrying electrode of the first transistor to an input terminal of the first semiconductor device.
14. The method of claim 13 further including coupling a resistor in series between the first current carrying electrode of the first transistor and a power supply terminal of the first semiconductor device.
15. The method of claim 8 wherein configuring the first transistor to receive the signal from the second transistor includes coupling a second current carrying electrode of the first transistor to receive an operating voltage.
16. The method of claim 8 wherein configuring the first transistor to receive the signal from the second transistor of the differential pair that is external to the first semiconductor device includes configuring the first transistor to operate in a linear region of the first transistor.
17. The method of claim 8 wherein configuring the first transistor includes configuring the first transistor as an emitter follower.
18. The method of claim 8 wherein configuring the first transistor includes configuring the first transistor as a source follower.