Double-sided extended drain field effect transistor
View Patent ↗A double-sided extended drain field effect transistor that includes a gate terminal overlying a channel region in a substrate. The substrate includes a drain region of a first carrier type that is laterally separated from the channel region by a first RESURF region of the first carrier type, and a source region of the first carrier type that is laterally separated from the channel region by a second RESURF region of the first carrier type. Regions of the first carrier type may also be disposed laterally adjacent to the source and drain regions on the opposite lateral side as compared to the RESURF regions. This configuration improves the reverse bias breakdown voltage of the transistor.
1. A method of using a double-sided extended drain field effect transistor that includes a substrate and a gate terminal overlying the substrate over a channel region in the substrate, wherein the substrate further comprises a drain region of a first carrier type that is laterally separated from the channel region by a first RESURF region of the first carrier type; and a source region of the first carrier type that is laterally separated from the channel region by a second RESURF region of the first carrier type, wherein the drain region, the source region, the first RESURF region and the second RESURF region are all disposed within a single well region of a second carrier type that is opposite the first carrier type, the well region being disposed within the substrate, the method comprising the following:
an act of applying a first reverse bias to a first interface between the source region of the first carrier type and a body region of a second carrier type; and
an act of applying a second reverse bias to a second interface between the drain region of the first carrier type and the body region of the second carrier type.
2. A method in accordance with claim 1 , wherein the first reverse bias is not sufficient to breakdown the first interface, but would be sufficient to cause breakdown of the first interface if the first RESURF region and any other RESURF region bordering the source region were not present.
3. A method in accordance with claim 2 , wherein the second reverse bias is not sufficient to breakdown the second interface, but would be sufficient to cause breakdown of the second interface if the second RESURF region and any other RESURF region bordering the drain region were not present.
4. A method in accordance with claim 1 , wherein the second reverse bias is not sufficient to breakdown the second interface, but would be sufficient to cause breakdown of the second interface if the second RESURF region and any other RESURF region bordering the drain region were not present.
5. A method in accordance with claim 1 , wherein the double-sided extended drain field effect transistor further includes a first region of the first carrier type disposed laterally adjacent to the drain region on the side opposite the first RESURF region and that is disposed within the well region of the second carrier type.
6. A method in accordance with claim 5 , wherein the double-sided extended drain field effect transistor further includes a second region of the first carrier type disposed laterally adjacent to the source region on the side opposite the second RESURF region and that is disposed within the well region of the second carrier type.
7. A method in accordance with claim 1 , wherein the double-sided extended drain field effect transistor further includes a region of the first carrier type disposed laterally adjacent to the source region on the side opposite the second RESURF region and that is disposed within the well region of the second carrier type.
8. A method in accordance with claim 1 , wherein the first carrier type is n-type and the second carrier type is p-type.
9. A method in accordance with claim 1 , wherein the first carrier type is p-type and the second carrier type is n-type.
10. A double-sided extended drain field effect transistor comprising:
a substrate;
a gate terminal overlying the substrate over a channel region in the substrate, wherein the substrate further comprises:
a drain region of a first carrier type that is laterally separated from the channel region and that is disposed within a well region of a second carrier type that is opposite the first carrier type, the well region being disposed within the substrate;
a first RESURF region of the first carrier type that laterally separates the drain region from the channel region and that is disposed within the well region of a second carrier type;
a source region of the first carrier type that is laterally separated from the channel region and that is disposed within the well region of the second carrier type;
a second RESURF region of the first carrier type that laterally separates the source region from the channel region and that is disposed within the well region of the second carrier type; and
a first region of the first carrier type disposed laterally adjacent to the drain region on the side opposite the first RESURF region and that is disposed within the well region of the second carrier type.
11. A double-sided extended drain field effect transistor in accordance with claim 10 , wherein the substrate further comprises:
a second region of the first carrier type disposed laterally adjacent to the source region on the side opposite the second RESURF region and that is disposed within the well region of the second carrier type.
12. A double-sided extended drain field effect transistor in accordance with claim 10 , wherein the first carrier type is n-type and the second carrier type is p-type.
13. A double-sided extended drain field effect transistor in accordance with claim 10 , wherein the first carrier type is p-type and the second carrier type is n-type.
14. A double-sided extended drain field effect transistor comprising:
a substrate;
a gate terminal overlying the substrate over a channel region in the substrate, wherein the substrate further comprises:
a drain region of a first carrier type that is laterally separated from the channel region and that is disposed within a well region of a second carrier type that is opposite the first carrier type, the well region being disposed within the substrate;
a first RESURF region of the first carrier type that laterally separates the drain region from the channel region and that is disposed within the well region of the second carrier type;
a source region of the first carrier type that is laterally separated from the channel region and that is disposed within the well region of the second carrier type;
a second RESURF region of the first carrier type that laterally separates the source region from the channel region and that is disposed within the well region of the second carrier type; and
a first region of the first carrier type disposed laterally adjacent to the source region on the side opposite the second RESURF region and that is disposed within the well region of the second carrier type.
15. A double-sided extended drain field effect transistor in accordance with claim 14 , wherein the first carrier type is n-type and the second carrier type is p-type.
16. A double-sided extended drain field effect transistor in accordance with claim 14 , wherein the first carrier type is p-type and the second carrier type is n-type.