Method for the production of a semiconductor substrate comprising a plurality of gate stacks on a semiconductor substrate, and corresponding semiconductor structure
View Patent ↗Method for the production of a semiconductor structure comprising a plurality of gate stacks on a semiconductor substrate which serve as control electrodes for a respective selection transistor of a corresponding memory cell comprising a storage capacitor. Gate stacks are provided next to one another on the substrate provided with a gate dielectric wherein the gate stacks have a lower first layer made of polysilicon, an overlying second layer made of metal silicide, and an upper layer made of silicon nitride. A sidewall oxide is formed on uncovered sidewalls of the first and second layers of the gate stacks, and at least partly the sidewall oxide is removed on those sidewalls of the gate stacks serving as a control electrode which are remote from the associated storage capacitor. Silicon nitride sidewall spacers are then formed on the gate stacks.
1. A method for the production of a semiconductor structure comprising a plurality of gate stacks on a semiconductor substrate, which serve as control electrodes for a respective selection transistor of a corresponding memory cell comprising a storage capacitor having the steps of:
a) providing the gate stacks next to one another on the semiconductor substrate provided with a gate dielectric, the gate stacks having a lower first layer made of polysilicon, an overlying second layer made of a metal silicide, in particular a tungsten silicide, and an upper third layer made of silicon nitride;
b) forming a sidewall oxide on uncovered sidewalls of the first and second layers of the gate stacks;
c) removing at least partly the sidewall oxide on those sidewalls of the gate stacks serving as a control electrode which are remote from the associated storage capacitor; and
e) forming silicon nitride sidewall spacers on the gate stacks.
2. The method as claimed in claim 1 , wherein the gate stacks are provided in parallel strip-type fashion on the semiconductor substrate.
3. The method as claimed in claim 2 , wherein the gate stacks are provided with approximately the same configuration and approximately the same spacing on the semiconductor substrate.
4. The method as claimed in claim 3 , wherein active regions of the selection transistors are provided in a self-aligning manner in the interspace between the gate stacks.
5. The method as claimed in claim 1 , wherein the removal of the sidewall oxide on the sidewalls of the gate stacks serving as a control electrode takes place using a mask.
6. The method as claimed in claim 1 , wherein the sidewall oxide is removed on opposite sidewalls of adjacent gate stacks above respective active regions which simultaneously serve as a connection for two selection transistors.
7. The method as claimed in claim 1 , wherein a respective bit line contact is formed between sidewalls of adjacent gate stacks with an at least partly removed sidewall oxide.
8. The method as claimed in claim 1 , wherein the gate stacks are created by carrying out an application and patterning of the first, the overlying second and the upper third layer on the gate dielectric.