Over-voltage tolerant bus hold circuit and method therefor

1. A method of forming an over-voltage bus hold circuit comprising:

coupling a first inverter and a second inverter as a latch;

configuring a switch to operably couple an operating voltage to the second inverter responsively to a signal input of the first inverter receiving an input signal that is approximately less than a value of the operating voltage;

coupling a pair of transistors in a current mirror configuration to receive the input signal and responsively form a current having a first value that is representative of the input signal having a value that is no less than the value of the operating voltage and to have a second value that is representative of the input signal having a value that is less than the value of the operating voltage; and

configuring the switch to operably decouple the operating voltage from the second inverter responsively to the first value of the current.

2. The method of claim 1 wherein configuring the switch to operably couple the operating voltage to the second inverter includes coupling the switch in series between an operating voltage input of the second inverter and the operating voltage.

3. The method of claim 1 wherein configuring the switch to operably decouple the operating voltage from the second inverter includes coupling a control input of the switch to receive a control signal that is representative of the input signal.

4. The method of claim 3 wherein coupling the control input of the switch to receive the control signal that is representative of the input signal includes coupling a first current carrying electrode of a first current mirror transistor of the pair of transistors in the current mirror configuration to receive the input signal and responsively form the control signal.

5. The method of claim 4 further including coupling a second current carrying electrode of the first current mirror transistor of the pair of transistors in the current mirror configuration to the control input of the switch.

6. The method of claim 1 wherein configuring the switch to operably decouple the operating voltage from the second inverter includes coupling a first P-channel MOS transistor in series between an operating voltage input of the second inverter and the operating voltage.

7. The method of claim 6 further including configuring a second P-channel MOS transistor to couple a body of the first P-channel MOS transistor to the operating voltage responsively to the first inverter receiving the input signal that is approximately less than the value of the operating voltage.

8. The method of claim 6 further including configuring a second P-channel MOS transistor to couple a body of the first P-channel MOS transistor to the operating voltage responsively to the first inverter receiving the input signal that is no less than the value of the operating voltage.

9. A method of operating a bus hold circuit comprising:

receiving an input signal having a voltage value that is approximately no less than an operating voltage of the bus hold circuit;

coupling the input signal to an output of a first inverter;

using a pair of current mirror coupled transistors to form a current having a first value that is representative of the input signal having the voltage value that is approximately no less than the operating voltage and having a second value that is representative of the input signal having a voltage value that is approximately less than the operating voltage; and

selectively disabling a switch to decouple the first inverter from the operating voltage.

10. The method of claim 9 further including receiving the input signal having the voltage value that is approximately less than the operating voltage of the bus hold circuit and responsively enabling the switch to couple the first inverter to the operating voltage.

11. The method of claim 9 wherein disabling the switch to decouple the first inverter from the operating voltage includes disabling a transistor to decouple the first inverter from the operating voltage and coupling a body of the transistor to receive the input signal.

12. The method of claim 9 wherein disabling the switch to decouple the first inverter from the operating voltage includes coupling a body of a first transistor of the first inverter to receive the input signal.

13. An over-voltage bus hold circuit comprising:

a first inverter having an signal input, a signal output, and an operating voltage input;

a switch operably coupled between the operating voltage input of the first inverter and an operating voltage terminal that is configured for receiving an operating voltage, the switch having a control input; and

a control circuit configured to enable the switch responsively to the signal output receiving a signal having a value that is approximately no less than the operating voltage, the control circuit including a first transistor configured to couple a body of the switch to the signal having the value that is approximately no less than the operating voltage responsively to the signal output receiving the signal having the value that is no less than the operating voltage, the first transistor having a first current carrying electrode coupled to the body of the switch, a body coupled to the body of the switch, a second current carrying electrode coupled to the signal output of the first inverter, a second transistor having a first current carrying electrode coupled to the body of the switch, a body coupled to the body of the switch, a second current carrying electrode coupled to receive the operating voltage, and a control electrode coupled to a control input of the switch.

14. The over-voltage bus hold circuit of claim 13 further including the control circuit configured to disable the switch responsively to the signal output receiving a signal having a value that is approximately less than the operating voltage.

15. The over-voltage bus hold circuit of claim 13 wherein the first inverter includes a first transistor having a body contact and also having a first current carrying electrode coupled to the operating voltage input.

16. The over-voltage bus hold circuit of claim 13 wherein the control circuit includes a current mirror having a third transistor, the third transistor having a first current carrying electrode coupled to receive the signal output of the first inverter, a second current carrying electrode coupled to the control input of the switch, a body coupled to the body of the switch, and a control electrode coupled to a control electrode of a fourth transistor that is a portion of the current mirror.

17. The over-voltage bus hold circuit of claim 16 wherein the current mirror includes a fifth transistor having a first current carrying electrode coupled to the second current carrying electrode of the third transistor, a control electrode, and a second current carrying electrode coupled to a voltage return, a sixth transistor having a control electrode coupled to the control electrode of the fifth transistor, a first current carrying electrode coupled to the voltage return, and a second current carrying electrode coupled to the control electrode, and a seventh transistor having a body coupled to the body of the switch, a control electrode coupled to the signal output of the first inverter, a first current carrying electrode coupled to the second current carrying electrode of the sixth transistor, and a second current carrying electrode coupled to a first current carrying electrode of the fourth transistor, and the fourth transistor having a body coupled to the body of the switch, and a second current carrying electrode coupled to receive the operating voltage.